From: 黄涛 Date: Tue, 23 Apr 2013 10:58:24 +0000 (+0800) Subject: rk: add show cpu and soc interface X-Git-Tag: firefly_0821_release~7230 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4906177e72aab5b7f305e876fc8ef20e9eab94c7;p=firefly-linux-kernel-4.4.55.git rk: add show cpu and soc interface --- diff --git a/arch/arm/plat-rk/Makefile b/arch/arm/plat-rk/Makefile index 0dc74c95bc74..c80ef0514c94 100755 --- a/arch/arm/plat-rk/Makefile +++ b/arch/arm/plat-rk/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FIQ_DEBUGGER) += rk_fiq_debugger.o obj-$(CONFIG_RK_EARLY_PRINTK) += early_printk.o ../kernel/debug.o obj-y += mem_reserve.o obj-y += config.o +obj-y += cpu.o obj-y += sram.o obj-y += iomux.o obj-$(CONFIG_DDR_TEST) += memtester.o ddr_test.o diff --git a/arch/arm/plat-rk/cpu.c b/arch/arm/plat-rk/cpu.c new file mode 100644 index 000000000000..139104aa64a1 --- /dev/null +++ b/arch/arm/plat-rk/cpu.c @@ -0,0 +1,68 @@ +#include +#include +#include + +static ssize_t show_type(struct sysdev_class *dev, struct sysdev_class_attribute *attr, char *buf) +{ + const char *type; + + if (cpu_is_rk3188()) + type = "rk3188"; + else if (cpu_is_rk3066b()) + type = "rk3066b"; + else if (cpu_is_rk30xx()) + type = "rk30xx"; + else if (cpu_is_rk2928()) + type = "rk2928"; + else + type = ""; + + return sprintf(buf, "%s\n", type); +} + +static SYSDEV_CLASS_ATTR(type, 0444, show_type, NULL); + +static ssize_t show_soc(struct sysdev_class *dev, struct sysdev_class_attribute *attr, char *buf) +{ + const char *soc; + + if (soc_is_rk3188plus()) + soc = "rk3188+"; + else if (soc_is_rk3188()) + soc = "rk3188"; + else if (soc_is_rk3168()) + soc = "rk3168"; + else if (soc_is_rk3028()) + soc = "rk3028"; + else if (soc_is_rk3066b()) + soc = "rk3066b"; + else if (soc_is_rk2928g()) + soc = "rk2928g"; + else if (soc_is_rk2928l()) + soc = "rk2928l"; + else if (soc_is_rk2926()) + soc = "rk2926"; + else if (soc_is_rk3066()) + soc = "rk3066"; + else if (soc_is_rk3068()) + soc = "rk3068"; + else if (soc_is_rk3000()) + soc = "rk3000"; + else + soc = ""; + + return sprintf(buf, "%s\n", soc); +} + +static SYSDEV_CLASS_ATTR(soc, 0444, show_soc, NULL); + +static int __init rk_cpu_init(void) +{ + int err; + + err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, &attr_type.attr); + err = sysfs_create_file(&cpu_sysdev_class.kset.kobj, &attr_soc.attr); + + return err; +} +late_initcall(rk_cpu_init); diff --git a/arch/arm/plat-rk/include/plat/cpu.h b/arch/arm/plat-rk/include/plat/cpu.h index 238dca0afd7b..11cf548a0c7a 100644 --- a/arch/arm/plat-rk/include/plat/cpu.h +++ b/arch/arm/plat-rk/include/plat/cpu.h @@ -24,7 +24,10 @@ static inline bool soc_is_rk2926(void) { return ((readl_relaxed(RK2928_GPIO3_BASE + 0x50) & 0x07) == SOC_RK2926); } + +static inline bool cpu_is_rk2928(void) { return true; } #else +static inline bool cpu_is_rk2928(void) { return false; } static inline bool soc_is_rk2928g(void) { return false; } static inline bool soc_is_rk2928l(void) { return false; } static inline bool soc_is_rk2926(void) { return false; } @@ -51,40 +54,72 @@ static inline bool cpu_is_rk3066b(void) && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030); } -static inline bool cpu_is_rk3188(void) -{ - return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042 - && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132 - && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313330 - && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030; -} -#else -static inline bool cpu_is_rk30xx(void) { return false; } -static inline bool cpu_is_rk3066b(void) { return false; } -static inline bool cpu_is_rk3188(void) { return false; } -#endif - -#ifdef CONFIG_ARCH_RK3066B static inline bool soc_is_rk3066b(void) { - return (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 0); + return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 0); } static inline bool soc_is_rk3108(void) { - return (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 1); + return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 1); } static inline bool soc_is_rk3168m(void) { - return (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 3); + return cpu_is_rk3066b() && (((readl_relaxed(RK30_GPIO1_BASE + GPIO_EXT_PORT) >> 22) & 3) == 3); +} + +static inline bool soc_is_rk3188(void) +{ + return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303132 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x31313330 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313030; +} + +static inline bool soc_is_rk3188plus(void) +{ + return readl_relaxed(RK30_ROM_BASE + 0x27f0) == 0x33313042 + && readl_relaxed(RK30_ROM_BASE + 0x27f4) == 0x32303133 + && readl_relaxed(RK30_ROM_BASE + 0x27f8) == 0x30313331 + && readl_relaxed(RK30_ROM_BASE + 0x27fc) == 0x56313031; } #else +static inline bool cpu_is_rk30xx(void) { return false; } +static inline bool cpu_is_rk3066b(void) { return false; } + static inline bool soc_is_rk3066b(void) { return false; } static inline bool soc_is_rk3108(void) { return false; } static inline bool soc_is_rk3168m(void) { return false; } + +static inline bool soc_is_rk3188(void) { return false; } +static inline bool soc_is_rk3188plus(void) { return false; } #endif + +static inline bool cpu_is_rk3188(void) +{ + return soc_is_rk3188plus() || soc_is_rk3188(); +} + static inline bool soc_is_rk3028(void) { return soc_is_rk3168m(); } static inline bool soc_is_rk3168(void) { return soc_is_rk3108(); } +#ifdef CONFIG_SOC_RK3000 +static inline bool soc_is_rk3000(void) { return true; } +#else +static inline bool soc_is_rk3000(void) { return false; } +#endif + +#ifdef CONFIG_SOC_RK3066 +static inline bool soc_is_rk3066(void) { return true; } +#else +static inline bool soc_is_rk3066(void) { return false; } +#endif + +#ifdef CONFIG_SOC_RK3068 +static inline bool soc_is_rk3068(void) { return true; } +#else +static inline bool soc_is_rk3068(void) { return false; } +#endif + #endif