From: Akira Hatanaka <ahatanaka@mips.com>
Date: Thu, 24 May 2012 18:32:33 +0000 (+0000)
Subject: Enable Mips16 compiler to compile a null program.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4a5a8949cd15bab98c6d73754b4d6376b34ee8af;p=oota-llvm.git

Enable Mips16 compiler to compile a null program.
First code from the Mips16 compiler. Includes trivial test program.

Patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157408 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td
index 4fec546c006..3672ea8b949 100644
--- a/lib/Target/Mips/Mips16InstrFormats.td
+++ b/lib/Target/Mips/Mips16InstrFormats.td
@@ -173,7 +173,7 @@ class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
 //===----------------------------------------------------------------------===//
 
-class FRR16<bits<5> op, bits<5> _funct, dag outs, dag ins, string asmstr,
+class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
             list<dag> pattern, InstrItinClass itin>:
             MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
 {
@@ -181,7 +181,7 @@ class FRR16<bits<5> op, bits<5> _funct, dag outs, dag ins, string asmstr,
   bits<3>  ry;
   bits<5>  funct;
 
-  let Opcode = op;
+  let Opcode = 0b11101;
   let funct  = _funct;
 
   let Inst{10-8} = rx;
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td
new file mode 100644
index 00000000000..7cbf2d4d427
--- /dev/null
+++ b/lib/Target/Mips/Mips16InstrInfo.td
@@ -0,0 +1,18 @@
+//===- Mips16InstrInfo.td - Target Description for Mips16  -*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes Mips16 instructions.
+//
+//===----------------------------------------------------------------------===//
+
+let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
+    isBarrier=1, hasCtrlDep=1, rx=0b000, ry=0b001 in
+def RET16 : FRR16 <0, (outs), (ins CPURAReg:$target),
+                   "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>,
+            Requires<[InMips16Mode]>;
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 6050d9aa4dc..d2a4387209f 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -140,6 +140,8 @@ def IsN64       :     Predicate<"Subtarget.isABI_N64()">,
                       AssemblerPredicate<"FeatureN64">;
 def NotN64      :     Predicate<"!Subtarget.isABI_N64()">,
                       AssemblerPredicate<"!FeatureN64">;
+def InMips16Mode :    Predicate<"Subtarget.inMips16Mode()">,
+                      AssemblerPredicate<"FeatureMips16">;
 def RelocStatic :     Predicate<"TM.getRelocationModel() == Reloc::Static">,
                       AssemblerPredicate<"FeatureMips32">;
 def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
@@ -147,8 +149,8 @@ def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
 def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">,
                       AssemblerPredicate<"FeatureMips32">;
 def HasStandardEncoding:
-               Predicate<"Subtarget.hasStandardEncoding()">,
-               AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
+  Predicate<"Subtarget.hasStandardEncoding()">,
+  AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
 
 //===----------------------------------------------------------------------===//
 // Instruction format superclass
@@ -256,7 +258,8 @@ def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
 
 // Mips Address Mode! SDNode frameindex could possibily be a match
 // since load and store instructions from stack used it.
-def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
+def addr :
+  ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
 
 //===----------------------------------------------------------------------===//
 // Pattern fragment for load/store
@@ -1211,4 +1214,4 @@ include "MipsCondMov.td"
 // Mips16
 
 include "Mips16InstrFormats.td"
-
+include "Mips16InstrInfo.td"
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 8a13bd13ea5..fb2f9c010e7 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -271,6 +271,8 @@ def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
   // Callee save
   S0, S1)>;
 
+def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>;
+
 
 // 64bit fp:
 // * FGR64  - 32 64-bit registers
diff --git a/test/CodeGen/Mips/null.ll b/test/CodeGen/Mips/null.ll
new file mode 100644
index 00000000000..a5e2c06576d
--- /dev/null
+++ b/test/CodeGen/Mips/null.ll
@@ -0,0 +1,10 @@
+; RUN: llc  -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
+
+
+define i32 @main() nounwind {
+entry:
+  ret i32 0
+
+; 16:	jr	$ra
+
+}