From: Jay Cheng Date: Fri, 6 Aug 2010 22:42:33 +0000 (-0400) Subject: [ARM] tegra: stingray: change UARTC clock source to PLL_P X-Git-Tag: firefly_0821_release~9834^2~722 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4a7c8dd336ffec102f9e6e49bd118094bec9b547;p=firefly-linux-kernel-4.4.55.git [ARM] tegra: stingray: change UARTC clock source to PLL_P Bluetooth requires 3Mpbs baud rate. Change UART clock source from clk_m (26000000) to pll_p (216000000). Signed-off-by: Jay Cheng --- diff --git a/arch/arm/mach-tegra/board-stingray.c b/arch/arm/mach-tegra/board-stingray.c index 4312cbbcd0ad..e68f54c77307 100644 --- a/arch/arm/mach-tegra/board-stingray.c +++ b/arch/arm/mach-tegra/board-stingray.c @@ -587,6 +587,7 @@ static struct tegra_i2c_platform_data stingray_i2c4_platform_data = { static __initdata struct tegra_clk_init_table stingray_clk_init_table[] = { /* name parent rate enabled */ { "uartb", "clk_m", 26000000, true}, + { "uartc", "pll_p", 216000000, false}, /*{ "emc", "pll_p", 0, true}, { "pll_m", NULL, 600000000, true}, { "emc", "pll_m", 600000000, false},*/