From: Ville Syrjälä Date: Thu, 24 Jan 2013 13:29:47 +0000 (+0200) Subject: drm/i915: Pipe palette registers need an offset on VLV X-Git-Tag: firefly_0821_release~3680^2~1036^2~36^2~41 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4b0599854b5669fbbb6c8b9a9463b550718bda11;p=firefly-linux-kernel-4.4.55.git drm/i915: Pipe palette registers need an offset on VLV Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2982a3baf0e6..693baf90db91 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1166,8 +1166,8 @@ * Palette regs */ -#define _PALETTE_A 0x0a000 -#define _PALETTE_B 0x0a800 +#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) +#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) /* MCH MMIO space */