From: Thierry Reding <treding@nvidia.com>
Date: Fri, 4 Apr 2014 13:55:15 +0000 (+0200)
Subject: clk: tegra: Fix enabling of PLLE
X-Git-Tag: firefly_0821_release~176^2~3857^2^2
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4ccc402ece35695dd2884ec0b652d52ae0230f13;p=firefly-linux-kernel-4.4.55.git

clk: tegra: Fix enabling of PLLE

When enabling the PLLE as its final step, clk_plle_enable() would
accidentally OR in the value previously written to the PLLE_SS_CTRL
register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 1187187a1cf2..7a1b70dac824 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -757,7 +757,7 @@ static int clk_plle_enable(struct clk_hw *hw)
 	val |= PLLE_SS_DISABLE;
 	writel(val, pll->clk_base + PLLE_SS_CTRL);
 
-	val |= pll_readl_base(pll);
+	val = pll_readl_base(pll);
 	val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
 	pll_writel_base(val, pll);