From: Brian Gaeke <gaeke@uiuc.edu>
Date: Fri, 18 Jun 2004 08:19:08 +0000 (+0000)
Subject: Mess around with allocation order. In particular, I think we ought to be
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4f217fdd10df91b8beefb1c86591597b43b769f6;p=oota-llvm.git

Mess around with allocation order. In particular, I think we ought to be
using the local & in regs first because they are not clobbered by calls.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14228 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td
index ca0bcdc171c..d8d130ccf54 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/lib/Target/Sparc/SparcRegisterInfo.td
@@ -69,10 +69,10 @@ let Namespace = "V8" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
-                                     O0, O1, O2, O3, O4, O5, O7,
-                                     L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
+                                     G1, G2, G3, G4, G5, G6, G7,
+                                     O0, O1, O2, O3, O4, O5, O7,
                                      // Non-allocatable regs
                                      O6, I6, I7, G0]> {
   let Methods = [{
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index ca0bcdc171c..d8d130ccf54 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -69,10 +69,10 @@ let Namespace = "V8" in {
 // FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
-def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
-                                     O0, O1, O2, O3, O4, O5, O7,
-                                     L0, L1, L2, L3, L4, L5, L6, L7,
+def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
+                                     G1, G2, G3, G4, G5, G6, G7,
+                                     O0, O1, O2, O3, O4, O5, O7,
                                      // Non-allocatable regs
                                      O6, I6, I7, G0]> {
   let Methods = [{