From: Bob Wilson Date: Fri, 21 Aug 2009 21:58:55 +0000 (+0000) Subject: Rename ARM "lane_cst" operands to "nohash_imm" since they are used for X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=4f38b383d5089c49489a9a56d8efd0eb76048b3f;p=oota-llvm.git Rename ARM "lane_cst" operands to "nohash_imm" since they are used for several things other than Neon vector lane numbers. For inline assembly operands with a "c" print code, check that they really are immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index bfeddfbe50d..21b42885d29 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -327,8 +327,8 @@ def addrmodepc : Operand, let MIOperandInfo = (ops GPR, i32imm); } -def lane_cst : Operand { - let PrintMethod = "printLaneOperand"; +def nohash_imm : Operand { + let PrintMethod = "printNoHashImmediate"; } //===----------------------------------------------------------------------===// @@ -581,7 +581,7 @@ def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), []>; def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), - (ins i32imm:$label, lane_cst:$id, pred:$p), + (ins i32imm:$label, nohash_imm:$id, pred:$p), Pseudo, IIC_iALUi, !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, " "(${label}_${id}-(", diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 1a68dce6370..4733ba0ffdc 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -1658,27 +1658,27 @@ def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), // VMOV : Vector Get Lane (move scalar to ARM core register) def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00, - (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), + (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, "vmov", ".s8\t$dst, $src[$lane]", [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src), imm:$lane))]>; def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01, - (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), + (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, "vmov", ".s16\t$dst, $src[$lane]", [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src), imm:$lane))]>; def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00, - (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), + (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, "vmov", ".u8\t$dst, $src[$lane]", [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src), imm:$lane))]>; def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01, - (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), + (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, "vmov", ".u16\t$dst, $src[$lane]", [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src), imm:$lane))]>; def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00, - (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane), + (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, "vmov", ".32\t$dst, $src[$lane]", [(set GPR:$dst, (extractelt (v2i32 DPR:$src), imm:$lane))]>; @@ -1715,17 +1715,17 @@ def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), let Constraints = "$src1 = $dst" in { def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst), - (ins DPR:$src1, GPR:$src2, lane_cst:$lane), + (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), NoItinerary, "vmov", ".8\t$dst[$lane], $src2", [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1), GPR:$src2, imm:$lane))]>; def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst), - (ins DPR:$src1, GPR:$src2, lane_cst:$lane), + (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), NoItinerary, "vmov", ".16\t$dst[$lane], $src2", [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1), GPR:$src2, imm:$lane))]>; def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst), - (ins DPR:$src1, GPR:$src2, lane_cst:$lane), + (ins DPR:$src1, GPR:$src2, nohash_imm:$lane), NoItinerary, "vmov", ".32\t$dst[$lane], $src2", [(set DPR:$dst, (insertelt (v2i32 DPR:$src1), GPR:$src2, imm:$lane))]>; @@ -1788,14 +1788,14 @@ def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), class VDUPLND op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty> : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0, - (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary, + (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>; class VDUPLNQ op19_18, bits<2> op17_16, string OpcodeStr, ValueType ResTy, ValueType OpTy> : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0, - (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary, + (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>; diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index aaff818ac53..b332042f574 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -632,7 +632,7 @@ def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, "adr$p $dst, #$label", []>; def tLEApcrelJT : T1I<(outs tGPR:$dst), - (ins i32imm:$label, lane_cst:$id, pred:$p), + (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, "adr$p $dst, #${label}_${id}", []>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index b5b92dddc36..5dd40546bc7 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -431,7 +431,7 @@ def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, "adr$p.w $dst, #$label", []>; def t2LEApcrelJT : T2XI<(outs GPR:$dst), - (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALUi, + (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, "adr$p.w $dst, #${label}_${id}", []>; // ADD r, sp, {so_imm|i12} diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index 3ef3fc5dbc1..4b0f92f6ce9 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -164,7 +164,7 @@ namespace { void printJTBlockOperand(const MachineInstr *MI, int OpNum); void printJT2BlockOperand(const MachineInstr *MI, int OpNum); void printTBAddrMode(const MachineInstr *MI, int OpNum); - void printLaneOperand(const MachineInstr *MI, int OpNum); + void printNoHashImmediate(const MachineInstr *MI, int OpNum); virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode); @@ -1010,7 +1010,7 @@ void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) { O << ']'; } -void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) { O << MI->getOperand(OpNum).getImm(); } @@ -1029,7 +1029,9 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, } // Fallthrough case 'c': // Don't print "#" before an immediate operand. - printLaneOperand(MI, OpNum); + if (!MI->getOperand(OpNum).isImm()) + return true; + printNoHashImmediate(MI, OpNum); return false; case 'P': // Print a VFP double precision register. printOperand(MI, OpNum);