From: xxx <xxx@rock-chips.com>
Date: Tue, 1 Jul 2014 07:43:34 +0000 (+0800)
Subject: suspend:resume arm errata818325
X-Git-Tag: firefly_0821_release~5013
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=519bbf15b9bdf097f215e72fd1a9eb9b8e81975f;p=firefly-linux-kernel-4.4.55.git

suspend:resume arm errata818325
---

diff --git a/arch/arm/mach-rockchip/pm-rk3288.c b/arch/arm/mach-rockchip/pm-rk3288.c
index 1e0e2a36e2b7..043f259b4a5e 100755
--- a/arch/arm/mach-rockchip/pm-rk3288.c
+++ b/arch/arm/mach-rockchip/pm-rk3288.c
@@ -810,8 +810,18 @@ static void gpio_ddr_dump_reg(int ports)
  {
      u32 l2ctlr;
      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
-         return l2ctlr;
+      return l2ctlr;
  }
+
+static inline u32 rkpm_armerrata_818325(void)
+{
+    u32 armerrata;
+    asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (armerrata));
+    return armerrata;
+}
+
+
+
 /**************************************sleep func**************************/
 
 void ddr_reg_save(uint32_t *pArg);
@@ -1060,11 +1070,23 @@ static void sram_code_data_save(u32 pwrmode)
         {   
             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume	
-            sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume	
-            sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume    
+            
+            sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=1;
+            sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325]=rkpm_armerrata_818325();//
+        
+            sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume	            
+            sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume  
+            #if 0
+            rkpm_ddr_printascii("l2&arm_errata--");   
+            rkpm_ddr_printhex(rkpm_l2_config());             
+            rkpm_ddr_printhex(rkpm_armerrata_818325());
+            rkpm_ddr_printascii("\n");  
+            #endif
         }
         else
         {
+            sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=0;
+            sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=0;       
             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
             return ;
         }
@@ -1259,13 +1281,19 @@ static void rkpm_save_setting(u32 ctrbits)
 }
 static void rkpm_save_setting_resume(void)
 {
+
+        #if 0
+        rkpm_ddr_printascii("l2&arm_errata--");   
+        rkpm_ddr_printhex(rkpm_l2_config());             
+        rkpm_ddr_printhex(rkpm_armerrata_818325());
+        rkpm_ddr_printascii("\n");            
+        #endif
                    
          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
         {
             sram_code_data_resume(rk3288_powermode); 
             rkpm_peri_resume(rk3288_powermode);
-        }
-         
+        }         
          rkpm_slp_mode_set_resume();       
 
 }
diff --git a/arch/arm/mach-rockchip/pm.h b/arch/arm/mach-rockchip/pm.h
old mode 100644
new mode 100755
index be9b61048257..b1e748e619da
--- a/arch/arm/mach-rockchip/pm.h
+++ b/arch/arm/mach-rockchip/pm.h
@@ -10,15 +10,22 @@
 // index data off in SLP_DATA_SAVE_BASE
 // it may be include in *.s ,so con't use enum type define
 
-#define RKPM_BOOTDATA_L2LTY_F             (0)  //save l2 latency val
-#define RKPM_BOOTDATA_L2LTY             (RKPM_BOOTDATA_L2LTY_F+1)
-#define RKPM_BOOTDATA_CPUSP            (RKPM_BOOTDATA_L2LTY+1)  //cpu sp addr
+
+
+#define RKPM_BOOTDATA_CPUSP            (0)  //cpu sp addr
 #define RKPM_BOOTDATA_CPUCODE       (RKPM_BOOTDATA_CPUSP+1)  //cpu resume fun,phy base
 #define RKPM_BOOTDATA_DDR_F            (RKPM_BOOTDATA_CPUCODE+1)  //ddr flag , 1 need to resume ddr ctr
 #define RKPM_BOOTDATA_DPLL_F          (RKPM_BOOTDATA_DDR_F+1) //ddr pll flag, 1  need to resume dpll
 #define RKPM_BOOTDATA_DDRCODE       (RKPM_BOOTDATA_DPLL_F+1) //ddr resume code ,phy base
 #define RKPM_BOOTDATA_DDRDATA       (RKPM_BOOTDATA_DDRCODE+1) //ddr resume data ,phy base
-#define RKPM_BOOTDATA_ARR_SIZE  (RKPM_BOOTDATA_DDRDATA+1)
+// for l2 resume
+#define RKPM_BOOTDATA_L2LTY_F             (RKPM_BOOTDATA_DDRDATA+1)  //save l2 latency val
+#define RKPM_BOOTDATA_L2LTY             (RKPM_BOOTDATA_L2LTY_F+1)
+// for arm errata 81835 resume
+#define RKPM_BOOTDATA_ARM_ERRATA_818325_F            (RKPM_BOOTDATA_L2LTY+1)  //save l2 latency val
+#define RKPM_BOOTDATA_ARM_ERRATA_818325             (RKPM_BOOTDATA_ARM_ERRATA_818325_F+1)
+
+#define RKPM_BOOTDATA_ARR_SIZE  (RKPM_BOOTDATA_ARM_ERRATA_818325+1)
 
 
 
diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S
old mode 100644
new mode 100755
index f1cd0efb485c..1839b5d598b9
--- a/arch/arm/mach-rockchip/sleep.S
+++ b/arch/arm/mach-rockchip/sleep.S
@@ -92,11 +92,21 @@ v7_invalidate_l1:
         ldr r5,8f     // resume data  offset ,from ram base
         add r5,r5,r1 // resume data addr
         
-        //l2
+        //l2 resume 
+        ldr r3 ,[r5,#(RKPM_BOOTDATA_L2LTY_F*4)] // l2 resume flags
+        cmp r3,#1
+        bne arm_errata__818325
         ldr r3 ,[r5,#(RKPM_BOOTDATA_L2LTY*4)]
-        mcr p15, 1, r3, c9, c0, 2
-
-        //sp
+        mcr p15, 1, r3, c9, c0, 2   
+        
+arm_errata__818325:
+        ldr r3 ,[r5,#(RKPM_BOOTDATA_ARM_ERRATA_818325_F*4)]
+        cmp r3,#1
+        bne sp_set
+        ldr r3 ,[r5,#(RKPM_BOOTDATA_ARM_ERRATA_818325*4)]
+        mcreq   p15, 0, r3, c15, c0, 1
+
+sp_set:        //sp
         ldr sp,[r5,#(RKPM_BOOTDATA_CPUSP*4)]   //sp      
         
 	ldr r3,[r5,#(RKPM_BOOTDATA_DDR_F*4)]   //get SLP_DDR_NEED_RES ,if it is 1 ,ddr need to reusme