From: Aaron Ballman <aaron@aaronballman.com>
Date: Wed, 11 Nov 2015 13:44:06 +0000 (+0000)
Subject: Silencing nine warnings for "enumeral and non-enumeral type in conditional expression... 
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=52525c09284a6497d2fab509e84cc708d87fe0e0;p=oota-llvm.git

Silencing nine warnings for "enumeral and non-enumeral type in conditional expression"; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252728 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp
index 21b912603be..7d257ee6afa 100644
--- a/lib/Target/X86/X86FrameLowering.cpp
+++ b/lib/Target/X86/X86FrameLowering.cpp
@@ -531,16 +531,24 @@ MachineInstr *X86FrameLowering::emitStackProbeInline(
   // registers. For the prolog expansion we use RAX, RCX and RDX.
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const TargetRegisterClass *RegClass = &X86::GR64RegClass;
-  const unsigned
-      SizeReg = InProlog ? X86::RAX : MRI.createVirtualRegister(RegClass),
-      ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
-      CopyReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
-      TestReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
-      FinalReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
-      RoundedReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
-      LimitReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
-      JoinReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
-      ProbeReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass);
+  const unsigned SizeReg = InProlog ? (unsigned)X86::RAX
+                                    : MRI.createVirtualRegister(RegClass),
+                 ZeroReg = InProlog ? (unsigned)X86::RCX
+                                    : MRI.createVirtualRegister(RegClass),
+                 CopyReg = InProlog ? (unsigned)X86::RDX
+                                    : MRI.createVirtualRegister(RegClass),
+                 TestReg = InProlog ? (unsigned)X86::RDX
+                                    : MRI.createVirtualRegister(RegClass),
+                 FinalReg = InProlog ? (unsigned)X86::RDX
+                                     : MRI.createVirtualRegister(RegClass),
+                 RoundedReg = InProlog ? (unsigned)X86::RDX
+                                       : MRI.createVirtualRegister(RegClass),
+                 LimitReg = InProlog ? (unsigned)X86::RCX
+                                     : MRI.createVirtualRegister(RegClass),
+                 JoinReg = InProlog ? (unsigned)X86::RCX
+                                    : MRI.createVirtualRegister(RegClass),
+                 ProbeReg = InProlog ? (unsigned)X86::RCX
+                                     : MRI.createVirtualRegister(RegClass);
 
   // SP-relative offsets where we can save RCX and RDX.
   int64_t RCXShadowSlot = 0;