From: Ville Syrjälä Date: Thu, 6 Jun 2013 10:09:32 +0000 (+0300) Subject: Revert "drm/i915: Include display_mmio_offset in sequencer index/data registers" X-Git-Tag: firefly_0821_release~176^2~5752^2~61^2~69 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5434fd926d1e4de5d82fcbd4e7e4698cc6575bdb;p=firefly-linux-kernel-4.4.55.git Revert "drm/i915: Include display_mmio_offset in sequencer index/data registers" We use port I/O for VGA register access, so adding display_mmio_offset is just wrong. This reverts commit 56a12a509296c87d6f149be86c6694d312b21d35. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 47a9de0d51cc..ff9f71af9347 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -147,15 +147,9 @@ #define VGA_MSR_MEM_EN (1<<1) #define VGA_MSR_CGA_MODE (1<<0) -/* - * SR01 is the only VGA register touched on non-UMS setups. - * VLV doesn't do UMS, so the sequencer index/data registers - * are the only VGA registers which need to include - * display_mmio_offset. - */ -#define VGA_SR_INDEX (dev_priv->info->display_mmio_offset + 0x3c4) +#define VGA_SR_INDEX 0x3c4 #define SR01 1 -#define VGA_SR_DATA (dev_priv->info->display_mmio_offset + 0x3c5) +#define VGA_SR_DATA 0x3c5 #define VGA_AR_INDEX 0x3c0 #define VGA_AR_VID_EN (1<<5)