From: Bill Schmidt Date: Mon, 20 Apr 2015 15:54:26 +0000 (+0000) Subject: [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txt X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=54f902e367ffe7e660a233e06b5e703773090fe9;p=oota-llvm.git [PowerPC] Add future work for vector insert/extract to README_ALTIVEC.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235309 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt index 1d5b0922a9f..e40c44b8272 100644 --- a/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/lib/Target/PowerPC/README_ALTIVEC.txt @@ -313,3 +313,17 @@ Opportunies to use instructions from PPCInstrVSX.td during code gen Related to this: we currently do not generate the lxvw4x instruction for either v4f32 or v4i32, probably because adding a dag pattern to the recognizer requires a single target type. This should probably be addressed in the PPCISelDAGToDAG logic. + +//===----------------------------------------------------------------------===// + +Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only for v2f64 with VSX available. We should create custom lowering support for the other vector types. Without this support, we generate sequences with load-hit-store hazards. + +v4f32 can be supported with VSX by shifting the correct element into big-endian lane 0, using xscvspdpn to produce a double-precision representation of the single-precision value in big-endian double-precision lane 0, and reinterpreting lane 0 as an FPR or vector-scalar register. + +v2i64 can be supported with VSX and P8Vector in the same manner as v2f64, followed by a direct move to a GPR. + +v4i32 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 1, using a direct move to a GPR, and sign-extending the 32-bit result to 64 bits. + +v8i16 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 3, using a direct move to a GPR, and sign-extending the 16-bit result to 64 bits. + +v16i8 can be supported with VSX and P8Vector by shifting the correct element into big-endian lane 7, using a direct move to a GPR, and sign-extending the 8-bit result to 64 bits.