From: chenxing <chenxing@rock-chips.com>
Date: Mon, 10 Sep 2012 02:47:21 +0000 (+0800)
Subject: rk2928: set gpu auto select parent to support 266/400MHz
X-Git-Tag: firefly_0821_release~8677^2
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5594f893e2dd6a975bebd19eef5ac76055828337;p=firefly-linux-kernel-4.4.55.git

rk2928: set gpu auto select parent to support 266/400MHz
---

diff --git a/arch/arm/mach-rk2928/clock_data.c b/arch/arm/mach-rk2928/clock_data.c
index 3f7263951a07..e77ae42b96cb 100644
--- a/arch/arm/mach-rk2928/clock_data.c
+++ b/arch/arm/mach-rk2928/clock_data.c
@@ -1670,8 +1670,8 @@ static struct clk clk_gpu_pre = {
 	.mode		= gate_mode,
 	.gate_idx	= CLK_GATE_GPU_PRE,
 	.recalc		= clksel_recalc_div,
-	//.set_rate	= clkset_rate_freediv_autosel_parents,
-	.set_rate	= clksel_set_rate_freediv,
+	.set_rate	= clkset_rate_freediv_autosel_parents,
+	//.set_rate	= clksel_set_rate_freediv,
 	.round_rate	= clk_freediv_round_autosel_parents_rate,
 	.clksel_con	= CRU_CLKSELS_CON(34),
 	CRU_SRC_SET(0x1, 8),	
@@ -2563,7 +2563,7 @@ static void __init rk2928_clock_common_init(unsigned long gpll_rate,unsigned lon
 	clk_set_rate_nolock(&aclk_vepu, 300*MHZ);
 	clk_set_rate_nolock(&aclk_vdpu, 300*MHZ);
 	//gpu auto sel
-	clk_set_parent_nolock(&clk_gpu_pre, &general_pll_clk);
+	//clk_set_parent_nolock(&clk_gpu_pre, &general_pll_clk);
 	
 	clk_set_parent_nolock(&clk_cpu_div, &general_pll_clk);