From: Chris Lattner <sabre@nondot.org>
Date: Tue, 7 Mar 2006 04:42:59 +0000 (+0000)
Subject: add a note
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5a63c47fb5fd610a98a3425f06a683833c30693b;p=oota-llvm.git

add a note


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26585 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt
index 050f6142912..8fad506f5cc 100644
--- a/lib/Target/PowerPC/README.txt
+++ b/lib/Target/PowerPC/README.txt
@@ -452,3 +452,17 @@ _test:
         srwi r3, r2, 24
         blr
 
+===-------------------------------------------------------------------------===
+
+On the G5, logical CR operations are more expensive in their three
+address form: ops that read/write the same register are half as expensive as
+those that read from two registers that are different from their destination.
+
+We should model this with two separate instructions.  The isel should generate
+the "two address" form of the instructions.  When the register allocator 
+detects that it needs to insert a copy due to the two-addresness of the CR
+logical op, it will invoke PPCInstrInfo::convertToThreeAddress.  At this point
+we can convert to the "three address" instruction, to save code space.
+
+This only matters when we start generating cr logical ops.
+