From: Vincent Lejeune Date: Tue, 1 Oct 2013 19:32:38 +0000 (+0000) Subject: R600: Enable -verify-machineinstrs in some tests. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5b00e833fabbf5bdf2973c63c39d4a0d0143853a;p=oota-llvm.git R600: Enable -verify-machineinstrs in some tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index 61437e90e62..8d3f740c3c5 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -28,7 +28,7 @@ using namespace llvm; AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) - : AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { } + : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { return RI; diff --git a/lib/Target/R600/AMDILInstrInfo.td b/lib/Target/R600/AMDILInstrInfo.td index f7d0bd5734e..0f0c88db935 100644 --- a/lib/Target/R600/AMDILInstrInfo.td +++ b/lib/Target/R600/AMDILInstrInfo.td @@ -118,15 +118,15 @@ class ILFormat pattern> // Multiclass Instruction formats //===--------------------------------------------------------------------===// // Multiclass that handles branch instructions -multiclass BranchConditional { +multiclass BranchConditional { def _i32 : ILFormat<(outs), - (ins brtarget:$target, GPRI32:$src0), + (ins brtarget:$target, rci:$src0), "; i32 Pseudo branch instruction", - [(Op bb:$target, GPRI32:$src0)]>; + [(Op bb:$target, (i32 rci:$src0))]>; def _f32 : ILFormat<(outs), - (ins brtarget:$target, GPRF32:$src0), + (ins brtarget:$target, rcf:$src0), "; f32 Pseudo branch instruction", - [(Op bb:$target, GPRF32:$src0)]>; + [(Op bb:$target, (f32 rcf:$src0))]>; } // Only scalar types should generate flow control diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 92aae63494b..b2c2f93dfe8 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -651,6 +651,11 @@ bool isJump(unsigned Opcode) { return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND; } +static bool isBranch(unsigned Opcode) { + return Opcode == AMDGPU::BRANCH || Opcode == AMDGPU::BRANCH_COND_i32 || + Opcode == AMDGPU::BRANCH_COND_f32; +} + bool R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -669,6 +674,10 @@ R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, return false; --I; } + // AMDGPU::BRANCH* instructions are only available after isel and are not + // handled + if (isBranch(I->getOpcode())) + return true; if (!isJump(static_cast(I)->getOpcode())) { return false; } diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index e92385dd1d3..f38fa5dc571 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -2238,7 +2238,7 @@ let isTerminator = 1, usesCustomInserter = 1, isBranch = 1, isBarrier = 1 in { def BRANCH : ILFormat<(outs), (ins brtarget:$target), "; Pseudo unconditional branch instruction", [(br bb:$target)]>; - defm BRANCH_COND : BranchConditional; + defm BRANCH_COND : BranchConditional; } //===---------------------------------------------------------------------===// diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td index 514427eb25c..6fec43c4d7a 100644 --- a/lib/Target/R600/R600RegisterInfo.td +++ b/lib/Target/R600/R600RegisterInfo.td @@ -138,8 +138,6 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32, (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>; -} // End isAllocatable = 0 - def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "KC0_%u_X", 128, 159))>; @@ -172,6 +170,8 @@ def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32, (interleave R600_KC1_X, R600_KC1_Y, R600_KC1_Z, R600_KC1_W)>; +} // End isAllocatable = 0 + def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "T%u_X", 0, 127), AR_X)>; @@ -192,6 +192,7 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add R600_TReg32, R600_ArrayBase, R600_Addr, + R600_KC0, R600_KC1, ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF, ALU_CONST, ALU_PARAM, OQAP )>; diff --git a/test/CodeGen/R600/schedule-fs-loop-nested-if.ll b/test/CodeGen/R600/schedule-fs-loop-nested-if.ll index ba9620c40a4..2a660943098 100644 --- a/test/CodeGen/R600/schedule-fs-loop-nested-if.ll +++ b/test/CodeGen/R600/schedule-fs-loop-nested-if.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-fs-loop-nested.ll b/test/CodeGen/R600/schedule-fs-loop-nested.ll index 5e875c49ab5..b917ec6413e 100644 --- a/test/CodeGen/R600/schedule-fs-loop-nested.ll +++ b/test/CodeGen/R600/schedule-fs-loop-nested.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-fs-loop.ll b/test/CodeGen/R600/schedule-fs-loop.ll index d142cacd433..d6c194b19b2 100644 --- a/test/CodeGen/R600/schedule-fs-loop.ll +++ b/test/CodeGen/R600/schedule-fs-loop.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-if-2.ll b/test/CodeGen/R600/schedule-if-2.ll index 6afd6772926..38aad1850f8 100644 --- a/test/CodeGen/R600/schedule-if-2.ll +++ b/test/CodeGen/R600/schedule-if-2.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-if.ll b/test/CodeGen/R600/schedule-if.ll index 347d92fd6a0..f960c932394 100644 --- a/test/CodeGen/R600/schedule-if.ll +++ b/test/CodeGen/R600/schedule-if.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() {