From: Bill Schmidt Date: Mon, 16 Sep 2013 17:25:12 +0000 (+0000) Subject: [PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5c616f91a5136295bf83850bc3610bd28756e58e;p=oota-llvm.git [PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit. Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which is a nop on PPC64. This is needed to keep the register class system happy, but on the fast-isel path it is not removed before emit as it is for DAG select. Ignore this op when emitting instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190795 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 59ba9c4af62..346a9beada9 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetOpcodes.h" using namespace llvm; STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); @@ -76,11 +77,17 @@ public: SmallVectorImpl &Fixups) const; void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { + // For fast-isel, a float COPY_TO_REGCLASS can survive this long. + // It's just a nop to keep the register classes happy, so don't + // generate anything. + unsigned Opcode = MI.getOpcode(); + if (Opcode == TargetOpcode::COPY_TO_REGCLASS) + return; + uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); // BL8_NOP etc. all have a size of 8 because of the following 'nop'. unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value! - unsigned Opcode = MI.getOpcode(); if (Opcode == PPC::BL8_NOP || Opcode == PPC::BLA8_NOP || Opcode == PPC::BL8_NOP_TLS) Size = 8;