From: Vikram S. Adve <vadve@cs.uiuc.edu>
Date: Fri, 27 Sep 2002 14:29:45 +0000 (+0000)
Subject: Modify operand order for Create{Sign,Zero}ExtensionInstructions.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5cededee9217804de91a5a55c9e38df06a239a4e;p=oota-llvm.git

Modify operand order for Create{Sign,Zero}ExtensionInstructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3960 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 6a1373174e0..993f2a2ffa1 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -497,10 +497,10 @@ UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
     { // sign- or zero-extend respectively
       storeVal = new TmpInstruction(storeType, val);
       if (val->getType()->isSigned())
-        CreateSignExtensionInstructions(target, F, val, 8*srcSize, storeVal,
+        CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
                                         mvec, mcfi);
       else
-        CreateZeroExtensionInstructions(target, F, val, 8*srcSize, storeVal,
+        CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
                                         mvec, mcfi);
     }
   MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
@@ -640,27 +640,27 @@ CreateBitExtensionInstructions(bool signExtend,
                                const TargetMachine& target,
                                Function* F,
                                Value* srcVal,
-                               unsigned int srcSizeInBits,
-                               Value* dest,
+                               Value* destVal,
+                               unsigned int numLowBits,
                                vector<MachineInstr*>& mvec,
                                MachineCodeForInstruction& mcfi)
 {
   MachineInstr* M;
-  assert(srcSizeInBits <= 32 &&
-         "Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled.");
 
-  if (srcSizeInBits < 32)
+  assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
+
+  if (numLowBits < 32)
     { // SLL is needed since operand size is < 32 bits.
-      TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
-                                                srcVal, dest,"make32");
+      TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
+                                                srcVal, destVal, "make32");
       mcfi.addTemp(tmpI);
-      M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-srcSizeInBits, tmpI);
+      M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
       mvec.push_back(M);
       srcVal = tmpI;
     }
 
   M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
-                                 srcVal, 32-srcSizeInBits, dest);
+                                 srcVal, 32-numLowBits, destVal);
   mvec.push_back(M);
 }
 
@@ -676,13 +676,13 @@ UltraSparcInstrInfo::CreateSignExtensionInstructions(
                                         const TargetMachine& target,
                                         Function* F,
                                         Value* srcVal,
-                                        unsigned int srcSizeInBits,
-                                        Value* dest,
+                                        Value* destVal,
+                                        unsigned int numLowBits,
                                         vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
-                                 srcSizeInBits, dest, mvec, mcfi);
+                                 destVal, numLowBits, mvec, mcfi);
 }
 
 
@@ -698,11 +698,11 @@ UltraSparcInstrInfo::CreateZeroExtensionInstructions(
                                         const TargetMachine& target,
                                         Function* F,
                                         Value* srcVal,
-                                        unsigned int srcSizeInBits,
-                                        Value* dest,
+                                        Value* destVal,
+                                        unsigned int numLowBits,
                                         vector<MachineInstr*>& mvec,
                                         MachineCodeForInstruction& mcfi) const
 {
   CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
-                                 srcSizeInBits, dest, mvec, mcfi);
+                                 destVal, numLowBits, mvec, mcfi);
 }
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 01315baa19e..fc99ae45137 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -194,8 +194,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
   virtual void CreateSignExtensionInstructions(const TargetMachine& target,
                                        Function* F,
                                        Value* srcVal,
-                                       unsigned int srcSizeInBits,
-                                       Value* dest,
+                                       Value* destVal,
+                                       unsigned int numLowBits,
                                        std::vector<MachineInstr*>& mvec,
                                        MachineCodeForInstruction& mcfi) const;
 
@@ -208,8 +208,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
   virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
                                        Function* F,
                                        Value* srcVal,
-                                       unsigned int srcSizeInBits,
-                                       Value* dest,
+                                       Value* destVal,
+                                       unsigned int numLowBits,
                                        std::vector<MachineInstr*>& mvec,
                                        MachineCodeForInstruction& mcfi) const;
 };