From: Duraid Madina Date: Mon, 11 Apr 2005 05:55:56 +0000 (+0000) Subject: assorted fixes: X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5ef2ec99297118681d3ac8fde4902830b4d1259a;p=oota-llvm.git assorted fixes: * clean up immediates (we use 14, 22 and 64 bit immediates now. sane.) * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0 * fix nasty thinko - didn't use two-address form of conditional add for extending bools to integers, so occasionally there would be garbage in the result. it's amazing how often zeros are just sitting around in registers ;) - this should fix a bunch of tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21221 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp index 2759301d6b0..2846a044a28 100644 --- a/lib/Target/IA64/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/IA64AsmPrinter.cpp @@ -225,14 +225,6 @@ namespace { } } - void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, - MVT::ValueType VT) { - O << (short)MI->getOperand(OpNo).getImmedValue(); - } - void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, - MVT::ValueType VT) { - O << (unsigned short)MI->getOperand(OpNo).getImmedValue(); - } void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) { int val=(unsigned int)MI->getOperand(OpNo).getImmedValue(); @@ -245,17 +237,11 @@ namespace { if(val>=8192) val=val-16384; // if negative, flip sign O << val; } - void printS21ImmOperand(const MachineInstr *MI, unsigned OpNo, - MVT::ValueType VT) { - O << (int)MI->getOperand(OpNo).getImmedValue(); // FIXME (21, not 32!) - } - void printS32ImmOperand(const MachineInstr *MI, unsigned OpNo, - MVT::ValueType VT) { - O << (int)MI->getOperand(OpNo).getImmedValue(); - } - void printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, + void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) { - O << (unsigned int)MI->getOperand(OpNo).getImmedValue(); + int val=(unsigned int)MI->getOperand(OpNo).getImmedValue(); + if(val>=2097152) val=val-4194304; // if negative, flip sign + O << val; } void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo, MVT::ValueType VT) { diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 07c536adf1d..996f722cbe7 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -639,28 +639,36 @@ unsigned ISel::SelectExpr(SDOperand N) { else // false: BuildMI(BB, IA64::CMPNE, 2, Result) .addReg(IA64::r0).addReg(IA64::r0); - return Result; + return Result; // early exit } - case MVT::i64: Opc = IA64::MOVLI32; break; + case MVT::i64: break; } int64_t immediate = cast(N)->getValue(); - if(immediate>>32) { // if our immediate really is big: - int highPart = immediate>>32; - int lowPart = immediate&0xFFFFFFFF; - unsigned dummy = MakeReg(MVT::i64); - unsigned dummy2 = MakeReg(MVT::i64); - unsigned dummy3 = MakeReg(MVT::i64); - - BuildMI(BB, IA64::MOVLI32, 1, dummy).addImm(highPart); - BuildMI(BB, IA64::SHLI, 2, dummy2).addReg(dummy).addImm(32); - BuildMI(BB, IA64::MOVLI32, 1, dummy3).addImm(lowPart); - BuildMI(BB, IA64::ADD, 2, Result).addReg(dummy2).addReg(dummy3); - } else { - BuildMI(BB, IA64::MOVLI32, 1, Result).addImm(immediate); + + if(immediate==0) { // if the constant is just zero, + BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r0); // just copy r0 + return Result; // early exit } - return Result; + if (immediate <= 8191 && immediate >= -8192) { + // if this constants fits in 14 bits, we use a mov the assembler will + // turn into: "adds rDest=imm,r0" (and _not_ "andl"...) + BuildMI(BB, IA64::MOVSIMM14, 1, Result).addSImm(immediate); + return Result; // early exit + } + + if (immediate <= 2097151 && immediate >= -2097152) { + // if this constants fits in 22 bits, we use a mov the assembler will + // turn into: "addl rDest=imm,r0" + BuildMI(BB, IA64::MOVSIMM22, 1, Result).addSImm(immediate); + return Result; // early exit + } + + /* otherwise, our immediate is big, so we use movl */ + uint64_t Imm = immediate; + BuildMI(BB, IA64::MOVLIMM64, 1, Result).addU64Imm(Imm); + return Result; } case ISD::UNDEF: { @@ -706,7 +714,7 @@ unsigned ISel::SelectExpr(SDOperand N) { // first load zero: BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0); // ...then conditionally (PR:Tmp1) add 1: - BuildMI(BB, IA64::CADDIMM22, 3, Result).addReg(dummy) + BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy) .addImm(1).addReg(Tmp1); return Result; // XXX early exit! } @@ -823,15 +831,16 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); return Result; // early exit } Tmp1 = SelectExpr(N.getOperand(0)); - Tmp2 = SelectExpr(N.getOperand(1)); if(DestType != MVT::f64) { // integer addition: switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) { case 1: // adding a constant that's 14 bits BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3); return Result; // early exit } // fallthrough and emit a reg+reg ADD: + Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2); } else { // this is a floating point addition + Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2); } return Result; @@ -868,7 +877,6 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); BuildMI(BB, IA64::FMS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); return Result; // early exit } - Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); if(DestType != MVT::f64) { // integer subtraction: switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) { @@ -876,8 +884,10 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2); return Result; // early exit } // fallthrough and emit a reg+reg SUB: + Tmp1 = SelectExpr(N.getOperand(0)); BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2); } else { // this is a floating point subtraction + Tmp1 = SelectExpr(N.getOperand(0)); BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2); } return Result; @@ -1311,9 +1321,20 @@ pC = pA OR pB case ISD::SETCC: { Tmp1 = SelectExpr(N.getOperand(0)); - Tmp2 = SelectExpr(N.getOperand(1)); + if (SetCCSDNode *SetCC = dyn_cast(Node)) { if (MVT::isInteger(SetCC->getOperand(0).getValueType())) { + + if(ConstantSDNode *CSDN = + dyn_cast(N.getOperand(1))) { + // if we are comparing against a constant zero + if(CSDN->getValue()==0) + Tmp2 = IA64::r0; // then we can just compare against r0 + else + Tmp2 = SelectExpr(N.getOperand(1)); + } else // not comparing against a constant + Tmp2 = SelectExpr(N.getOperand(1)); + switch (SetCC->getCondition()) { default: assert(0 && "Unknown integer comparison!"); case ISD::SETEQ: @@ -1351,6 +1372,20 @@ pC = pA OR pB else { // if not integer, should be FP. FIXME: what about bools? ;) assert(SetCC->getOperand(0).getValueType() != MVT::f32 && "error: SETCC should have had incoming f32 promoted to f64!\n"); + + if(ConstantFPSDNode *CFPSDN = + dyn_cast(N.getOperand(1))) { + + // if we are comparing against a constant +0.0 or +1.0 + if(CFPSDN->isExactlyValue(+0.0)) + Tmp2 = IA64::F0; // then we can just compare against f0 + else if(CFPSDN->isExactlyValue(+1.0)) + Tmp2 = IA64::F1; // or f1 + else + Tmp2 = SelectExpr(N.getOperand(1)); + } else // not comparing against a constant + Tmp2 = SelectExpr(N.getOperand(1)); + switch (SetCC->getCondition()) { default: assert(0 && "Unknown FP comparison!"); case ISD::SETEQ: @@ -1836,7 +1871,7 @@ void ISel::Select(SDOperand N) { unsigned dummy3 = MakeReg(MVT::i64); unsigned dummy4 = MakeReg(MVT::i64); BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0); - BuildMI(BB, IA64::CADDIMM22, 3, dummy4) + BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4) .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1; BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4); } @@ -1858,7 +1893,7 @@ void ISel::Select(SDOperand N) { unsigned dummy3 = MakeReg(MVT::i64); unsigned dummy4 = MakeReg(MVT::i64); BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0); - BuildMI(BB, IA64::CADDIMM22, 3, dummy4) + BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4) .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1; BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4); } diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index 6177c9ba996..c57673379fe 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -22,15 +22,8 @@ def s8imm : Operand { def s14imm : Operand { let PrintMethod = "printS14ImmOperand"; } -def s16imm : Operand; -def s21imm : Operand { - let PrintMethod = "printS21ImmOperand"; -} -def u32imm : Operand { - let PrintMethod = "printU32ImmOperand"; -} -def s32imm : Operand { - let PrintMethod = "printS32ImmOperand"; +def s22imm : Operand { + let PrintMethod = "printS22ImmOperand"; } def u64imm : Operand { let PrintMethod = "printU64ImmOperand"; @@ -92,13 +85,11 @@ let isTwoAddress = 1 in { "($qp) cmp.eq $dst, p0 = $src3, $src4;;">; } -def MOVI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm), +def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm), "mov $dst = $imm;;">; -def MOVLI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm), - "movl $dst = $imm;;">; -def MOVLSI32 : AForm<0x03, 0x0b, (ops GR:$dst, s32imm:$imm), - "movl $dst = $imm;;">; -def MOVLI64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm), +def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm), + "mov $dst = $imm;;">; +def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm), "movl $dst = $imm;;">; def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), @@ -109,15 +100,15 @@ def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "xor $dst = $src1, $src2;;">; def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "shl $dst = $src1, $src2;;">; -def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm), - "shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21 +def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), + "shl $dst = $src1, $imm;;">; def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "shr.u $dst = $src1, $src2;;">; -def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm), +def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), "shr.u $dst = $src1, $imm;;">; def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), "shr $dst = $src1, $src2;;">; -def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm), +def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), "shr $dst = $src1, $imm;;">; def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), @@ -193,17 +184,17 @@ def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2), def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm), "adds $dst = $imm, $src1;;">; -def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm), +def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm), "add $dst = $imm, $src1;;">; -def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp), +def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), "($qp) add $dst = $imm, $src1;;">; let isTwoAddress = 1 in { def TPCADDIMM22 : AForm<0x03, 0x0b, - (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp), + (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp), "($qp) add $dst = $imm, $dst;;">; def TPCMPIMM8NE : AForm<0x03, 0x0b, - (ops PR:$dst, PR:$src1, s21imm:$imm, GR:$src2, PR:$qp), + (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp), "($qp) cmp.ne $dst , p0 = $imm, $src2;;">; } diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 18ffcec246b..a5b0572dbd4 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -189,7 +189,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const //fix up the old: MI.SetMachineOperandReg(i, IA64::r22); MachineInstr* nMI; - nMI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(Offset); + nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset); MBB.insert(II, nMI); nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister) .addReg(IA64::r22); @@ -280,7 +280,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes); MBB.insert(MBBI, MI); } else { // we use r22 as a scratch register here - MI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(-NumBytes); + MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes); // FIXME: MOVLSI32 expects a _u_32imm MBB.insert(MBBI, MI); // first load the decrement into r22 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); @@ -328,7 +328,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes); MBB.insert(MBBI, MI); } else { - MI=BuildMI(IA64::MOVLI32, 1, IA64::r22).addImm(NumBytes); + MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes); MBB.insert(MBBI, MI); MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22); MBB.insert(MBBI, MI);