From: Bruno Cardoso Lopes <bruno.cardoso@gmail.com>
Date: Mon, 12 Sep 2011 22:59:23 +0000 (+0000)
Subject: Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=5fc48100ee2f94dc0d4bef354b06d7373c3770a2;p=oota-llvm.git

Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
destination types are equal!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 0d86902e01d..63d97980a4f 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -4250,11 +4250,11 @@ let Predicates = [HasAVX] in {
   // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
   let AddedComplexity = 20 in {
     def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
-              (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
+              (VMOVZDI2PDIrm addr:$src)>;
     def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
-              (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
+              (VMOVZDI2PDIrm addr:$src)>;
     def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
-              (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
+              (VMOVZDI2PDIrm addr:$src)>;
   }
   // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
   def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
@@ -4347,11 +4347,11 @@ let Predicates = [HasSSE2], AddedComplexity = 20 in {
 
 let Predicates = [HasAVX], AddedComplexity = 20 in {
   def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
-            (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
+            (VMOVZQI2PQIrm addr:$src)>;
   def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
-            (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
+            (VMOVZQI2PQIrm addr:$src)>;
   def : Pat<(v2i64 (X86vzload addr:$src)),
-            (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
+            (VMOVZQI2PQIrm addr:$src)>;
 }
 
 //===---------------------------------------------------------------------===//
@@ -4392,9 +4392,9 @@ let AddedComplexity = 20 in {
   }
   let Predicates = [HasAVX] in {
     def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
-              (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIrm addr:$src), sub_xmm)>;
+              (VMOVZPQILo2PQIrm addr:$src)>;
     def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
-              (SUBREG_TO_REG (i64 0), (MOVZPQILo2PQIrr VR128:$src), sub_xmm)>;
+              (VMOVZPQILo2PQIrr VR128:$src)>;
   }
 }
 
diff --git a/test/CodeGen/X86/avx-basic.ll b/test/CodeGen/X86/avx-basic.ll
index d085f5d6cdb..edbdc06a1c9 100644
--- a/test/CodeGen/X86/avx-basic.ll
+++ b/test/CodeGen/X86/avx-basic.ll
@@ -91,3 +91,17 @@ entry:
   ret <8 x i32> %shuffle
 }
 
+;;; Don't crash on movd
+; CHECK: _VMOVZQI2PQI
+; CHECK: vmovd (%
+define <8 x i32> @VMOVZQI2PQI([0 x float]* nocapture %aFOO) nounwind {
+allocas:
+  %ptrcast.i33.i = bitcast [0 x float]* %aFOO to i32*
+  %val.i34.i = load i32* %ptrcast.i33.i, align 4
+  %ptroffset.i22.i992 = getelementptr [0 x float]* %aFOO, i64 0, i64 1
+  %ptrcast.i23.i = bitcast float* %ptroffset.i22.i992 to i32*
+  %val.i24.i = load i32* %ptrcast.i23.i, align 4
+  %updatedret.i30.i = insertelement <8 x i32> undef, i32 %val.i34.i, i32 1
+  ret <8 x i32> %updatedret.i30.i
+}
+