From: Chris Lattner <sabre@nondot.org>
Date: Thu, 28 Feb 2008 05:44:20 +0000 (+0000)
Subject: fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=61273d55e9ce068fef5dfcddb65e5ad9c1f4772e;p=oota-llvm.git

fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47706 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index f7cb9b84726..cc24abf7286 100644
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -7,6 +7,7 @@ To-do
 * We can fold small constant offsets into the %hi/%lo references to constant
   pool addresses as well.
 * When in V9 mode, register allocate %icc[0-3].
+* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
 * Emit the 'Branch on Integer Register with Prediction' instructions.  It's
   not clear how to write a pattern for this though:
 
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index faa3d3bbd97..40fa95c294b 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -218,6 +218,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 
+  // FIXME: Sparc provides these multiplies, but we don't have them yet.
+  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
+    
   // We don't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);