From: 黄涛 <huangtao@rock-chips.com>
Date: Thu, 30 Jun 2011 06:25:55 +0000 (+0800)
Subject: rk29: clock: display power domain is buggy, always keep it on
X-Git-Tag: firefly_0821_release~10149
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=61a22905a56cc613509b910c69ce84fd94837b59;p=firefly-linux-kernel-4.4.55.git

rk29: clock: display power domain is buggy, always keep it on
---

diff --git a/arch/arm/mach-rk29/clock.c b/arch/arm/mach-rk29/clock.c
index de4bfb85b062..6c66caecef86 100755
--- a/arch/arm/mach-rk29/clock.c
+++ b/arch/arm/mach-rk29/clock.c
@@ -1879,6 +1879,7 @@ static struct clk pd_vcodec = {
 
 static int pd_display_mode(struct clk *clk, int on)
 {
+#if 0	/* display power domain is buggy, always keep it on.  */
 	if (on) {
 		u32 gate, gate2;
 
@@ -1911,6 +1912,7 @@ static int pd_display_mode(struct clk *clk, int on)
 	} else {
 		pmu_set_power_domain(PD_DISPLAY, false);
 	}
+#endif
 
 	return 0;
 }
@@ -2606,7 +2608,7 @@ void __init rk29_clock_init2(enum periph_pll ppll_rate, enum codec_pll cpll_rate
 
 	rk29_clock_common_init(ppll_rate, cpll_rate);
 
-	printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz (20110617)\n",
+	printk(KERN_INFO "Clocking rate (apll/dpll/cpll/gpll/core/aclk_cpu/hclk_cpu/pclk_cpu/aclk_periph/hclk_periph/pclk_periph): %ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld/%ld MHz (20110630)\n",
 	       arm_pll_clk.rate / MHZ, ddr_pll_clk.rate / MHZ, codec_pll_clk.rate / MHZ, general_pll_clk.rate / MHZ, clk_core.rate / MHZ,
 	       aclk_cpu.rate / MHZ, hclk_cpu.rate / MHZ, pclk_cpu.rate / MHZ, aclk_periph.rate / MHZ, hclk_periph.rate / MHZ, pclk_periph.rate / MHZ);
 }