From: WeiYong Bi <bivvy.bi@rock-chips.com>
Date: Thu, 13 Jul 2017 07:12:14 +0000 (+0800)
Subject: arm64: dts: rockchip: rk3366: export MIPI DPHY PLL clock
X-Git-Tag: release-20171130_firefly~4^2~91
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=62fd23412357a855ad9d0d0e44e76dbc3707585b;hp=fd964decbc83699d2e4fb7d76ba192640292dcb6;p=firefly-linux-kernel-4.4.55.git

arm64: dts: rockchip: rk3366: export MIPI DPHY PLL clock

Change-Id: I99a4c252f877ff36a16f991ee2e94bb110401e47
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 67ce4befdb6b..47388e8cdb13 100644
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -1007,8 +1007,8 @@
 		compatible = "rockchip,rk3366-mipi-dsi";
 		reg = <0x0 0xff960000 0x0 0x4000>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_MIPI_DSI0>;
-		clock-names = "pclk";
+		clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
+		clock-names = "pclk", "hs_clk";
 		resets = <&cru SRST_MIPIDSI0>;
 		reset-names = "apb";
 		phys = <&mipi_dphy>;
@@ -1041,6 +1041,8 @@
 		reg = <0x0 0xff968000 0x0 0x4000>;
 		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
 		clock-names = "ref", "pclk";
+		clock-output-names = "mipi_dphy_pll";
+		#clock-cells = <0>;
 		resets = <&cru SRST_MIPIDPHYTX>;
 		reset-names = "apb";
 		#phy-cells = <0>;