From: 黄涛 <huangtao@rock-chips.com>
Date: Wed, 26 Sep 2012 06:04:10 +0000 (+0800)
Subject: rk30: pm: fix pll power off
X-Git-Tag: firefly_0821_release~8570
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=63c5a07d89e0904db024941cd188b376eebb7519;p=firefly-linux-kernel-4.4.55.git

rk30: pm: fix pll power off
---

diff --git a/arch/arm/mach-rk30/pm.c b/arch/arm/mach-rk30/pm.c
index a6bf959e8918..cccf0e5cb0f1 100644
--- a/arch/arm/mach-rk30/pm.c
+++ b/arch/arm/mach-rk30/pm.c
@@ -245,8 +245,10 @@ static void pm_pll_wait_lock(int pll_idx)
 }
 
 #define power_on_pll(id) \
-	cru_writel(PLL_PWR_DN_W_MSK|PLL_PWR_ON,PLL_CONS((id),3));\
+	cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_ON, PLL_CONS((id), 3));\
 	pm_pll_wait_lock((id))
+#define power_off_pll(id) \
+	cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_DN, PLL_CONS((id), 3))
 
 #define DDR_SAVE_SP(save_sp)		do { save_sp = ddr_save_sp(((unsigned long)SRAM_DATA_END & (~7))); } while (0)
 #define DDR_RESTORE_SP(save_sp)		do { ddr_save_sp(save_sp); } while (0)
@@ -568,7 +570,7 @@ static int rk30_pm_enter(suspend_state_t state)
 	//cpll
 	cru_writel(PLL_MODE_SLOW(CPLL_ID), CRU_MODE_CON);
 	cpll_con3 = cru_readl(PLL_CONS(CPLL_ID, 3));
-	cru_writel(PLL_PWR_DN_MSK | PLL_PWR_DN, PLL_CONS(CPLL_ID, 3));
+	power_off_pll(CPLL_ID);
 
 	//gpll
 	cru_writel(PLL_MODE_SLOW(GPLL_ID), CRU_MODE_CON);
@@ -577,7 +579,7 @@ static int rk30_pm_enter(suspend_state_t state)
 		   | CRU_W_MSK_SETBITS(0, PERI_HCLK_DIV_OFF, PERI_HCLK_DIV_MASK)
 		   | CRU_W_MSK_SETBITS(0, PERI_PCLK_DIV_OFF, PERI_PCLK_DIV_MASK)
 		   , CRU_CLKSELS_CON(10));
-	cru_writel(PLL_PWR_DN_MSK | PLL_PWR_DN, PLL_CONS(GPLL_ID, 3));
+	power_off_pll(GPLL_ID);
 
 	//apll
 	clk_sel0 = cru_readl(CRU_CLKSELS_CON(0));
@@ -596,7 +598,7 @@ static int rk30_pm_enter(suspend_state_t state)
 		   | ACLK_PCLK_W_MSK | ACLK_PCLK_11
 		   | AHB2APB_W_MSK | AHB2APB_11
 		   , CRU_CLKSELS_CON(1));
-	cru_writel(PLL_PWR_DN_W_MSK | PLL_PWR_DN, PLL_CONS(APLL_ID, 3));
+	power_off_pll(APLL_ID);
 
 	sram_printch('3');
 	rk30_pwm_suspend_voltage_set();