From: 黄涛 Date: Wed, 8 Aug 2012 03:25:30 +0000 (+0800) Subject: rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles X-Git-Tag: firefly_0821_release~8912^2~39 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=64340b93df27c256053ab01a0e5dafabd1fe1d8f;p=firefly-linux-kernel-4.4.55.git rk2928: l2 data ram latency, write 1 cycle, read 3 cycles, setup 2 cycles --- diff --git a/arch/arm/mach-rk2928/common.c b/arch/arm/mach-rk2928/common.c index 5585deb22ce0..1236dca8f1e4 100644 --- a/arch/arm/mach-rk2928/common.c +++ b/arch/arm/mach-rk2928/common.c @@ -49,8 +49,8 @@ static void __init rk2928_l2_cache_init(void) writel_relaxed(L2_LY_SET(1,L2_LY_SP_OFF) |L2_LY_SET(1,L2_LY_RD_OFF) |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_TAG_LATENCY_CTRL); - writel_relaxed(L2_LY_SET(4,L2_LY_SP_OFF) - |L2_LY_SET(6,L2_LY_RD_OFF) + writel_relaxed(L2_LY_SET(2,L2_LY_SP_OFF) + |L2_LY_SET(3,L2_LY_RD_OFF) |L2_LY_SET(1,L2_LY_WR_OFF), RK2928_L2C_BASE + L2X0_DATA_LATENCY_CTRL); /* L2X0 Prefetch Control */