From: dkl <dkl@rock-chips.com>
Date: Tue, 13 May 2014 02:24:07 +0000 (+0800)
Subject: clk: rk3288: set BW 20 when GPLL is 297m for HDMI
X-Git-Tag: firefly_0821_release~5299
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=654827f3f3c48bb4eacfe1e26a42ab4e329c0646;p=firefly-linux-kernel-4.4.55.git

clk: rk3288: set BW 20 when GPLL is 297m for HDMI
---

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 24f87c1f142c..51c10fd440d6 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1,5 +1,6 @@
 #include <linux/slab.h>
 #include <asm/io.h>
+#include <linux/rockchip/cpu.h>
 
 #include "clk-ops.h"
 #include "clk-pll.h"
@@ -679,6 +680,15 @@ static int clk_pll_set_rate_3188plus(struct clk_hw *hw, unsigned long rate,
 		clk_set++;
 	}
 
+	if (cpu_is_rk3288() && (rate == 297*MHZ)) {
+		if((strncmp(__clk_get_name(hw->clk), "clk_gpll",
+			strlen("clk_gpll")) == 0)) {
+
+			printk("rk3288 set GPLL BW 20 for HDMI!\n");
+			clk_set->pllcon2 = RK3188_PLL_CLK_BWADJ_SET(20);
+		}
+	}
+
 	if (clk_set->rate == rate) {
 		ret = _pll_clk_set_rate_3188plus(clk_set, hw);
 		clk_debug("pll %s set rate=%lu OK!\n", __clk_get_name(hw->clk),