From: Chris Lattner Date: Sun, 27 Nov 2011 06:10:54 +0000 (+0000) Subject: remove some old autoupgrade logic X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=663aebf8d65ce649d8a888a2a29493fe649b5c5d;p=oota-llvm.git remove some old autoupgrade logic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145167 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/VMCore/AutoUpgrade.cpp b/lib/VMCore/AutoUpgrade.cpp index 7b4a8f7ddf4..2fb1b8a0534 100644 --- a/lib/VMCore/AutoUpgrade.cpp +++ b/lib/VMCore/AutoUpgrade.cpp @@ -107,38 +107,6 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { } break; - case 'x': { - const char *NewFnName = NULL; - // This fixes the poorly named crc32 intrinsics. - if (Name == "x86.sse42.crc32.8") - NewFnName = "llvm.x86.sse42.crc32.32.8"; - else if (Name == "x86.sse42.crc32.16") - NewFnName = "llvm.x86.sse42.crc32.32.16"; - else if (Name == "x86.sse42.crc32.32") - NewFnName = "llvm.x86.sse42.crc32.32.32"; - else if (Name == "x86.sse42.crc64.8") - NewFnName = "llvm.x86.sse42.crc32.64.8"; - else if (Name == "x86.sse42.crc64.64") - NewFnName = "llvm.x86.sse42.crc32.64.64"; - - if (NewFnName) { - F->setName(NewFnName); - NewFn = F; - return true; - } - - // Calls to these instructions are transformed into unaligned loads. - if (Name == "x86.sse.loadu.ps" || Name == "x86.sse2.loadu.dq" || - Name == "x86.sse2.loadu.pd") - return true; - - // Calls to these instructions are transformed into nontemporal stores. - if (Name == "x86.sse.movnt.ps" || Name == "x86.sse2.movnt.dq" || - Name == "x86.sse2.movnt.pd" || Name == "x86.sse2.movnt.i") - return true; - - break; - } } // This may not belong here. This function is effectively being overloaded @@ -176,54 +144,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { assert(F && "CallInst has no function associated with it."); if (!NewFn) { - if (F->getName() == "llvm.x86.sse.loadu.ps" || - F->getName() == "llvm.x86.sse2.loadu.dq" || - F->getName() == "llvm.x86.sse2.loadu.pd") { - // Convert to a native, unaligned load. - Type *VecTy = CI->getType(); - Type *IntTy = IntegerType::get(C, 128); - IRBuilder<> Builder(C); - Builder.SetInsertPoint(CI->getParent(), CI); - - Value *BC = Builder.CreateBitCast(CI->getArgOperand(0), - PointerType::getUnqual(IntTy), - "cast"); - LoadInst *LI = Builder.CreateLoad(BC, CI->getName()); - LI->setAlignment(1); // Unaligned load. - BC = Builder.CreateBitCast(LI, VecTy, "new.cast"); - - // Fix up all the uses with our new load. - if (!CI->use_empty()) - CI->replaceAllUsesWith(BC); - - // Remove intrinsic. - CI->eraseFromParent(); - } else if (F->getName() == "llvm.x86.sse.movnt.ps" || - F->getName() == "llvm.x86.sse2.movnt.dq" || - F->getName() == "llvm.x86.sse2.movnt.pd" || - F->getName() == "llvm.x86.sse2.movnt.i") { - IRBuilder<> Builder(C); - Builder.SetInsertPoint(CI->getParent(), CI); - - Module *M = F->getParent(); - SmallVector Elts; - Elts.push_back(ConstantInt::get(Type::getInt32Ty(C), 1)); - MDNode *Node = MDNode::get(C, Elts); - - Value *Arg0 = CI->getArgOperand(0); - Value *Arg1 = CI->getArgOperand(1); - - // Convert the type of the pointer to a pointer to the stored type. - Value *BC = Builder.CreateBitCast(Arg0, - PointerType::getUnqual(Arg1->getType()), - "cast"); - StoreInst *SI = Builder.CreateStore(Arg1, BC); - SI->setMetadata(M->getMDKindID("nontemporal"), Node); - SI->setAlignment(16); - - // Remove intrinsic. - CI->eraseFromParent(); - } else if (F->getName().startswith("llvm.atomic.cmp.swap")) { + if (F->getName().startswith("llvm.atomic.cmp.swap")) { IRBuilder<> Builder(C); Builder.SetInsertPoint(CI->getParent(), CI); Value *Val = Builder.CreateAtomicCmpXchg(CI->getArgOperand(0), diff --git a/test/Assembler/AutoUpgradeIntrinsics.ll b/test/Assembler/AutoUpgradeIntrinsics.ll index daffa3d3af9..d64d0774534 100644 --- a/test/Assembler/AutoUpgradeIntrinsics.ll +++ b/test/Assembler/AutoUpgradeIntrinsics.ll @@ -2,37 +2,6 @@ ; RUN: llvm-as < %s | llvm-dis | FileCheck %s -declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readnone -declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone -declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone -define void @test_loadu(i8* %a, double* %b) { - %v0 = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a) - %v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a) - %v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b) - -; CHECK: load i128* {{.*}}, align 1 -; CHECK: load i128* {{.*}}, align 1 -; CHECK: load i128* {{.*}}, align 1 - ret void -} - -declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind readnone -declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x double>) nounwind readnone -declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind readnone -declare void @llvm.x86.sse2.movnt.i(i8*, i32) nounwind readnone - -define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D) { -; CHECK: store{{.*}}nontemporal - call void @llvm.x86.sse.movnt.ps(i8* %B, <4 x float> %A) -; CHECK: store{{.*}}nontemporal - call void @llvm.x86.sse2.movnt.dq(i8* %B, <2 x double> %C) -; CHECK: store{{.*}}nontemporal - call void @llvm.x86.sse2.movnt.pd(i8* %B, <2 x double> %C) -; CHECK: store{{.*}}nontemporal - call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D) - ret void -} - declare void @llvm.prefetch(i8*, i32, i32) nounwind define void @p(i8* %ptr) { diff --git a/test/Bitcode/sse42_crc32.ll b/test/Bitcode/sse42_crc32.ll deleted file mode 100644 index ddb108d1462..00000000000 --- a/test/Bitcode/sse42_crc32.ll +++ /dev/null @@ -1,44 +0,0 @@ -; Check to make sure old CRC32 intrinsics are auto-upgraded correctly. -; Auto-upgrade happens when parsing a .bc or a .ll file. Thus, leave the test -; case as a .ll file so we can see what's going on. -; -; Rdar: 9472944 -; -; RUN: opt < %s -S | FileCheck %s - -; crc32.8 should upgrade to crc32.32.8 -; CHECK: i32 @llvm.x86.sse42.crc32.32.8( -; CHECK-NOT: i32 @llvm.x86.sse42.crc32.8( - -; crc32.16 should upgrade to crc32.32.16 -; CHECK: i32 @llvm.x86.sse42.crc32.32.16( -; CHECK-NOT: i32 @llvm.x86.sse42.crc32.16( - -; crc32.32 should upgrade to crc32.32.32 -; CHECK: i32 @llvm.x86.sse42.crc32.32.32( -; CHECK-NOT: i32 @llvm.x86.sse42.crc32.32( - -; crc64.8 should upgrade to crc32.64.8 -; CHECK: i64 @llvm.x86.sse42.crc32.64.8( -; CHECK-NOT: i64 @llvm.x86.sse42.crc64.8( - -; crc64.64 should upgrade to crc32.64.64 -; CHECK: i64 @llvm.x86.sse42.crc32.64.64( -; CHECK-NOT: i64 @llvm.x86.sse42.crc64.64( - - -define void @foo() nounwind readnone ssp { -entry: - %0 = call i32 @llvm.x86.sse42.crc32.8(i32 0, i8 0) - %1 = call i32 @llvm.x86.sse42.crc32.16(i32 0, i16 0) - %2 = call i32 @llvm.x86.sse42.crc32.32(i32 0, i32 0) - %3 = call i64 @llvm.x86.sse42.crc64.8(i64 0, i8 0) - %4 = call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 0) - ret void -} - -declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind readnone -declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind readnone -declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind readnone -declare i64 @llvm.x86.sse42.crc64.8(i64, i8) nounwind readnone -declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index df12b71dba5..57e73121549 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -245,34 +245,6 @@ define <2 x double> @test_x86_sse2_div_sd(<2 x double> %a0, <2 x double> %a1) { declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind readnone -define <16 x i8> @test_x86_sse2_loadu_dq(i8* %a0) { - ; CHECK: movl - ; CHECK: vmovups - %res = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a0) ; <<16 x i8>> [#uses=1] - ret <16 x i8> %res -} -declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readonly - - -define <2 x double> @test_x86_sse2_loadu_pd(i8* %a0) { - ; CHECK: movl - ; CHECK: vmovups - %res = call <2 x double> @llvm.x86.sse2.loadu.pd(i8* %a0) ; <<2 x double>> [#uses=1] - ret <2 x double> %res -} -declare <2 x double> @llvm.x86.sse2.loadu.pd(i8*) nounwind readonly - - -define void @test_x86_sse2_maskmov_dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) { - ; CHECK: pushl - ; CHECK: movl - ; CHECK: vmaskmovdqu - ; CHECK: popl - call void @llvm.x86.sse2.maskmov.dqu(<16 x i8> %a0, <16 x i8> %a1, i8* %a2) - ret void -} -declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind - define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) { ; CHECK: vmaxpd @@ -314,28 +286,6 @@ define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) { declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone -define void @test_x86_sse2_movnt_dq(i8* %a0, <2 x i64> %a1) { - ; CHECK: test_x86_sse2_movnt_dq - ; CHECK: movl - ; CHECK: vmovntdq - ; add operation forces the execution domain. - %a2 = add <2 x i64> %a1, - call void @llvm.x86.sse2.movnt.dq(i8* %a0, <2 x i64> %a2) - ret void -} -declare void @llvm.x86.sse2.movnt.dq(i8*, <2 x i64>) nounwind - - -define void @test_x86_sse2_movnt_pd(i8* %a0, <2 x double> %a1) { - ; CHECK test_x86_sse2_movnt_pd - ; CHECK: movl - ; CHECK: vmovntpd - ; fadd operation forces the execution domain. - %a2 = fadd <2 x double> %a1, - call void @llvm.x86.sse2.movnt.pd(i8* %a0, <2 x double> %a2) - ret void -} -declare void @llvm.x86.sse2.movnt.pd(i8*, <2 x double>) nounwind define <2 x double> @test_x86_sse2_mul_sd(<2 x double> %a0, <2 x double> %a1) { @@ -967,14 +917,6 @@ define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) { declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone -define <2 x i64> @test_x86_sse41_movntdqa(i8* %a0) { - ; CHECK: movl - ; CHECK: vmovntdqa - %res = call <2 x i64> @llvm.x86.sse41.movntdqa(i8* %a0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %res -} -declare <2 x i64> @llvm.x86.sse41.movntdqa(i8*) nounwind readonly - define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK: vmpsadbw @@ -1524,14 +1466,6 @@ define void @test_x86_sse_ldmxcsr(i8* %a0) { declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind -define <4 x float> @test_x86_sse_loadu_ps(i8* %a0) { - ; CHECK: movl - ; CHECK: vmovups - %res = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a0) ; <<4 x float>> [#uses=1] - ret <4 x float> %res -} -declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readonly - define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vmaxps @@ -1573,14 +1507,6 @@ define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) { declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone -define void @test_x86_sse_movnt_ps(i8* %a0, <4 x float> %a1) { - ; CHECK: movl - ; CHECK: vmovntps - call void @llvm.x86.sse.movnt.ps(i8* %a0, <4 x float> %a1) - ret void -} -declare void @llvm.x86.sse.movnt.ps(i8*, <4 x float>) nounwind - define <4 x float> @test_x86_sse_mul_ss(<4 x float> %a0, <4 x float> %a1) { ; CHECK: vmulss @@ -2019,34 +1945,6 @@ define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) { declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly -define <32 x i8> @test_x86_avx_loadu_dq_256(i8* %a0) { - ; CHECK: vmovdqu - %a1 = call <32 x i8> @llvm.x86.avx.loadu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1] - ; add operation forces the execution domain. - %res = add <32 x i8> %a1, - ret <32 x i8> %res -} -declare <32 x i8> @llvm.x86.avx.loadu.dq.256(i8*) nounwind readonly - - -define <4 x double> @test_x86_avx_loadu_pd_256(i8* %a0) { - ; CHECK: vmovupd - %a1 = call <4 x double> @llvm.x86.avx.loadu.pd.256(i8* %a0) ; <<4 x double>> [#uses=1] - ; add operation forces the execution domain. - %res = fadd <4 x double> %a1, - ret <4 x double> %res -} -declare <4 x double> @llvm.x86.avx.loadu.pd.256(i8*) nounwind readonly - - -define <8 x float> @test_x86_avx_loadu_ps_256(i8* %a0) { - ; CHECK: vmovups - %res = call <8 x float> @llvm.x86.avx.loadu.ps.256(i8* %a0) ; <<8 x float>> [#uses=1] - ret <8 x float> %res -} -declare <8 x float> @llvm.x86.avx.loadu.ps.256(i8*) nounwind readonly - - define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x double> %a1) { ; CHECK: vmaskmovpd %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -2159,31 +2057,9 @@ define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) { declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone -define void @test_x86_avx_movnt_dq_256(i8* %a0, <4 x i64> %a1) { - ; CHECK: vmovntdq - ; add operation forces the execution domain. - %a2 = add <4 x i64> %a1, - call void @llvm.x86.avx.movnt.dq.256(i8* %a0, <4 x i64> %a2) - ret void -} -declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind - -define void @test_x86_avx_movnt_pd_256(i8* %a0, <4 x double> %a1) { - ; CHECK: vmovntpd - %a2 = fadd <4 x double> %a1, - call void @llvm.x86.avx.movnt.pd.256(i8* %a0, <4 x double> %a2) - ret void -} -declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind -define void @test_x86_avx_movnt_ps_256(i8* %a0, <8 x float> %a1) { - ; CHECK: vmovntps - call void @llvm.x86.avx.movnt.ps.256(i8* %a0, <8 x float> %a1) - ret void -} -declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {