From: Anton Korobeynikov Date: Tue, 15 Jan 2008 07:02:33 +0000 (+0000) Subject: For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=66fac79b899904ddd82e5ee354a6d370d80230f6;p=oota-llvm.git For PR1839: add initial support for __builtin_trap. llvm-gcc part is missed as well as PPC codegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46001 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index 47e3feb1388..30823833b79 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -563,6 +563,9 @@ namespace ISD { // chain as output. TRAMPOLINE, + // TRAP - Trapping instruction + TRAP, + // BUILTIN_OP_END - This must be the last enum value in this list. BUILTIN_OP_END }; diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index 94e5670c96b..703b794eb1c 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -266,6 +266,8 @@ def int_init_trampoline : Intrinsic<[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty, // def int_flt_rounds : Intrinsic<[llvm_i32_ty]>, GCCBuiltin<"__builtin_flt_rounds">; +def int_trap : Intrinsic<[llvm_void_ty]>, + GCCBuiltin<"__builtin_trap">; //===----------------------------------------------------------------------===// // Target-specific intrinsics diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index dd7c0e9f33a..8e9cd742339 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3733,6 +3733,25 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Result = DAG.getConstant(1, VT); break; } + } + case ISD::TRAP: { + MVT::ValueType VT = Node->getValueType(0); + switch (TLI.getOperationAction(Node->getOpcode(), VT)) { + default: assert(0 && "This action not supported for this op yet!"); + case TargetLowering::Custom: + Result = TLI.LowerOperation(Op, DAG); + if (Result.Val) break; + // Fall Thru + case TargetLowering::Legal: + // If this operation is not supported, lower it to 'abort()' call + SDOperand Chain = LegalizeOp(Node->getOperand(0)); + TargetLowering::ArgListTy Args; + std::pair CallResult = + TLI.LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, + DAG.getExternalSymbol("abort", MVT::Other), Args, DAG); + Result = CallResult.second; + break; + } } } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 22065156497..381e9dec646 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3770,7 +3770,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::BUILD_PAIR: return "build_pair"; case ISD::STACKSAVE: return "stacksave"; case ISD::STACKRESTORE: return "stackrestore"; - + case ISD::TRAP: return "trap"; + // Block memory operations. case ISD::MEMSET: return "memset"; case ISD::MEMCPY: return "memcpy"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 2934345b603..67da406e7e7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2932,6 +2932,11 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); return 0; } + + case Intrinsic::trap: { + DAG.setRoot(DAG.getNode(ISD::TRAP, MVT::Other, getRoot())); + return 0; + } } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 84502524481..0587dfa664c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -294,6 +294,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); + setOperationAction(ISD::TRAP, MVT::Other, Custom); + // VASTART needs to be custom lowered to use the VarArgsFrameIndex setOperationAction(ISD::VASTART , MVT::Other, Custom); setOperationAction(ISD::VAARG , MVT::Other, Expand); @@ -4948,6 +4950,10 @@ SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) { ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal); } +SDOperand X86TargetLowering::LowerTRAP(SDOperand Op, SelectionDAG &DAG) { + return DAG.getNode(X86ISD::TRAP, MVT::Other, Op.getOperand(0)); +} + SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) { MVT::ValueType VT = Op.getValueType(); MVT::ValueType OpVT = VT; @@ -5052,6 +5058,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG); case ISD::CTLZ: return LowerCTLZ(Op, DAG); case ISD::CTTZ: return LowerCTTZ(Op, DAG); + case ISD::TRAP: return LowerTRAP(Op, DAG); // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands. case ISD::READCYCLECOUNTER: @@ -5091,6 +5098,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { case X86ISD::CALL: return "X86ISD::CALL"; case X86ISD::TAILCALL: return "X86ISD::TAILCALL"; case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; + case X86ISD::TRAP: return "X86ISD::TRAP"; case X86ISD::CMP: return "X86ISD::CMP"; case X86ISD::COMI: return "X86ISD::COMI"; case X86ISD::UCOMI: return "X86ISD::UCOMI"; diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 64324f3dc59..959e6102151 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -197,7 +197,10 @@ namespace llvm { TC_RETURN, // Store FP control world into i16 memory - FNSTCW16m + FNSTCW16m, + + // Trapping instruction + TRAP }; } @@ -484,6 +487,7 @@ namespace llvm { SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG); SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG); SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG); + SDOperand LowerTRAP(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG); SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG); SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG); diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 02fc0772ecd..f9bdfc4f8bd 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -57,6 +57,8 @@ def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; +def SDT_X86TRAP : SDTypeProfile<0, 0, []>; + def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>; def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>; def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; @@ -107,6 +109,9 @@ def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, [SDNPHasChain, SDNPOptInFlag]>; +def X86trap : SDNode<"X86ISD::TRAP", SDT_X86TRAP, + [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>; + //===----------------------------------------------------------------------===// // X86 Operand Definitions. // @@ -484,6 +489,11 @@ let Defs = [RAX, RDX] in def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB; +let isBarrier = 1, hasCtrlDep = 1 in { +// FIXME: Should use 0x0F0B opcode +def TRAP : I<0, RawFrm, (outs), (ins), "ud2", [(X86trap)]>; +} + //===----------------------------------------------------------------------===// // Input/Output Instructions... //