From: Joerg Sonnenberger Date: Tue, 18 Aug 2015 21:31:46 +0000 (+0000) Subject: Load/store instructions for floating points with address space require SparcV9. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6774e25ec62734b08fa5f66b1798c0315e7d5f70;p=oota-llvm.git Load/store instructions for floating points with address space require SparcV9. To properly handle this, define the *a instructions as separate instruction classes by refactoring the LoadA and StoreA multiclasses. Move the instruction tests into the sparcv9 file to test the difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245360 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 3875979290f..02b3f080c2f 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -283,15 +283,19 @@ multiclass Load Op3Val, SDPatternOperator OpNode, [(set Ty:$dst, (OpNode ADDRri:$addr))]>; } +// TODO: Instructions of the LoadASR class are currently asm only; hooking up +// CodeGen's address spaces to use these is a future task. +class LoadASR Op3Val, SDPatternOperator OpNode, + RegisterClass RC, ValueType Ty> : + F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), + !strconcat(OpcStr, "a [$addr] $asi, $dst"), + []>; + // LoadA multiclass - As above, but also define alternate address space variant multiclass LoadA Op3Val, bits<6> LoadAOp3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : Load { - // TODO: The LD*Arr instructions are currently asm only; hooking up - // CodeGen's address spaces to use these is a future task. - def Arr : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), - !strconcat(OpcStr, "a [$addr] $asi, $dst"), - []>; + def Arr : LoadASR; } // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. @@ -307,14 +311,18 @@ multiclass Store Op3Val, SDPatternOperator OpNode, [(OpNode Ty:$rd, ADDRri:$addr)]>; } -multiclass StoreA Op3Val, bits<6> StoreAOp3Val, +// TODO: Instructions of the StoreASR class are currently asm only; hooking up +// CodeGen's address spaces to use these is a future task. +class StoreASR Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : - Store { - // TODO: The ST*Arr instructions are currently asm only; hooking up - // CodeGen's address spaces to use these is a future task. - def Arr : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), + F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), !strconcat(OpcStr, "a $rd, [$addr] $asi"), []>; + +multiclass StoreA Op3Val, bits<6> StoreAOp3Val, + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : + Store { + def Arr : StoreASR; } //===----------------------------------------------------------------------===// @@ -412,10 +420,16 @@ let DecoderMethod = "DecodeLoadIntPair" in defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32>; // Section B.2 - Load Floating-point Instructions, p. 92 -let DecoderMethod = "DecodeLoadFP" in - defm LDF : LoadA<"ld", 0b100000, 0b110000, load, FPRegs, f32>; -let DecoderMethod = "DecodeLoadDFP" in - defm LDDF : LoadA<"ldd", 0b100011, 0b110011, load, DFPRegs, f64>; +let DecoderMethod = "DecodeLoadFP" in { + defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; + def LDFArr : LoadASR<"ld", 0b110000, load, FPRegs, f32>, + Requires<[HasV9]>; +} +let DecoderMethod = "DecodeLoadDFP" in { + defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; + def LDDFArr : LoadASR<"ldd", 0b110011, load, DFPRegs, f64>, + Requires<[HasV9]>; +} let DecoderMethod = "DecodeLoadQFP" in defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>, Requires<[HasV9, HasHardQuad]>; @@ -431,12 +445,18 @@ let DecoderMethod = "DecodeStoreIntPair" in defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>; // Section B.5 - Store Floating-point Instructions, p. 97 -let DecoderMethod = "DecodeStoreFP" in - defm STF : StoreA<"st", 0b100100, 0b110100, store, FPRegs, f32>; -let DecoderMethod = "DecodeStoreDFP" in - defm STDF : StoreA<"std", 0b100111, 0b110111, store, DFPRegs, f64>; +let DecoderMethod = "DecodeStoreFP" in { + defm STF : Store<"st", 0b100100, store, FPRegs, f32>; + def STFArr : StoreASR<"st", 0b110100, store, FPRegs, f32>, + Requires<[HasV9]>; +} +let DecoderMethod = "DecodeStoreDFP" in { + defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; + def STDFArr : StoreASR<"std", 0b110111, store, DFPRegs, f64>, + Requires<[HasV9]>; +} let DecoderMethod = "DecodeStoreQFP" in - defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, + defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, Requires<[HasV9, HasHardQuad]>; // Section B.8 - SWAP Register with Memory Instruction diff --git a/test/MC/Sparc/sparc-fp-instructions.s b/test/MC/Sparc/sparc-fp-instructions.s index 30ef1d50cff..64f1538cb91 100644 --- a/test/MC/Sparc/sparc-fp-instructions.s +++ b/test/MC/Sparc/sparc-fp-instructions.s @@ -138,32 +138,12 @@ fdtox %f0, %f4 fqtox %f0, %f4 - ! CHECK: lda [%l0] 240, %f29 ! encoding: [0xfb,0x84,0x1e,0x00] ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00] - lda [%l0] 0xf0, %f29 - ld [%l0], %f29 - - ! CHECK: ldda [%l0] 240, %f48 ! encoding: [0xe3,0x9c,0x1e,0x00] ! CHECK: ldd [%l0], %f48 ! encoding: [0xe3,0x1c,0x00,0x00] - ldda [%l0] 0xf0, %f48 + ld [%l0], %f29 ldd [%l0], %f48 - ! CHECK: ldqa [%l0] 240, %f48 ! encoding: [0xe3,0x94,0x1e,0x00] - ! CHECK: ldq [%l0], %f48 ! encoding: [0xe3,0x14,0x00,0x00] - ldqa [%l0] 0xf0, %f48 - ldq [%l0], %f48 - - ! CHECK: sta %f29, [%l0] 240 ! encoding: [0xfb,0xa4,0x1e,0x00] ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00] - sta %f29, [%l0] 0xf0 - st %f29, [%l0] - - ! CHECK: stda %f48, [%l0] 240 ! encoding: [0xe3,0xbc,0x1e,0x00] ! CHECK: std %f48, [%l0] ! encoding: [0xe3,0x3c,0x00,0x00] - stda %f48, [%l0] 0xf0 + st %f29, [%l0] std %f48, [%l0] - - ! CHECK: stqa %f48, [%l0] 240 ! encoding: [0xe3,0xb4,0x1e,0x00] - ! CHECK: stq %f48, [%l0] ! encoding: [0xe3,0x34,0x00,0x00] - stqa %f48, [%l0] 0xf0 - stq %f48, [%l0] diff --git a/test/MC/Sparc/sparcv9-instructions.s b/test/MC/Sparc/sparcv9-instructions.s index f9877dd1107..b663dae6231 100644 --- a/test/MC/Sparc/sparcv9-instructions.s +++ b/test/MC/Sparc/sparcv9-instructions.s @@ -52,3 +52,41 @@ ! V8-NEXT: lduwa [%i0 + %l6] 131, %o2 ! V9: lda [%i0+%l6] 131, %o2 ! encoding: [0xd4,0x86,0x10,0x76] lduwa [%i0 + %l6] 131, %o2 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: lda [%l0] 0xf0, %f29 + ! V9: lda [%l0] 240, %f29 ! encoding: [0xfb,0x84,0x1e,0x00] + lda [%l0] 0xf0, %f29 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: ldda [%l0] 0xf0, %f48 + ! V9: ldda [%l0] 240, %f48 ! encoding: [0xe3,0x9c,0x1e,0x00] + ldda [%l0] 0xf0, %f48 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: ldqa [%l0] 0xf0, %f48 + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: ldq [%l0], %f48 + ! V9: ldqa [%l0] 240, %f48 ! encoding: [0xe3,0x94,0x1e,0x00] + ! V9: ldq [%l0], %f48 ! encoding: [0xe3,0x14,0x00,0x00] + ldqa [%l0] 0xf0, %f48 + ldq [%l0], %f48 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: sta %f29, [%l0] 0xf0 + ! V9: sta %f29, [%l0] 240 ! encoding: [0xfb,0xa4,0x1e,0x00] + sta %f29, [%l0] 0xf0 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: stda %f48, [%l0] 0xf0 + ! V9: stda %f48, [%l0] 240 ! encoding: [0xe3,0xbc,0x1e,0x00] + stda %f48, [%l0] 0xf0 + + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: stqa %f48, [%l0] 0xf0 + ! V8: error: instruction requires a CPU feature not currently enabled + ! V8-NEXT: stq %f48, [%l0] + ! V9: stqa %f48, [%l0] 240 ! encoding: [0xe3,0xb4,0x1e,0x00] + ! V9: stq %f48, [%l0] ! encoding: [0xe3,0x34,0x00,0x00] + stqa %f48, [%l0] 0xf0 + stq %f48, [%l0]