From: Alkis Evlogimenos Date: Tue, 17 Feb 2004 15:33:14 +0000 (+0000) Subject: Add OR and XOR memory operand support. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=68bff8e15db12aa565818914cf7e452171f13e3a;p=oota-llvm.git Add OR and XOR memory operand support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11549 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp index 3e0af70717c..4d52b74d3fc 100644 --- a/lib/Target/X86/PeepholeOptimizer.cpp +++ b/lib/Target/X86/PeepholeOptimizer.cpp @@ -156,6 +156,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, case X86::ADDmi16: case X86::ADDmi32: case X86::SUBmi16: case X86::SUBmi32: case X86::ANDmi16: case X86::ANDmi32: + case X86::ORmi16: case X86::ORmi32: + case X86::XORmi16: case X86::XORmi32: assert(MI->getNumOperands() == 5 && "These should all have 5 operands!"); if (MI->getOperand(4).isImmediate()) { int Val = MI->getOperand(4).getImmedValue(); @@ -170,6 +172,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, case X86::SUBmi32: Opcode = X86::SUBmi32b; break; case X86::ANDmi16: Opcode = X86::ANDmi16b; break; case X86::ANDmi32: Opcode = X86::ANDmi32b; break; + case X86::ORmi16: Opcode = X86::ORmi16b; break; + case X86::ORmi32: Opcode = X86::ORmi32b; break; + case X86::XORmi16: Opcode = X86::XORmi16b; break; + case X86::XORmi32: Opcode = X86::XORmi32b; break; } unsigned R0 = MI->getOperand(0).getReg(); unsigned Scale = MI->getOperand(1).getImmedValue(); diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 40a53b609cc..d26099ebf4f 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -379,24 +379,51 @@ def ANDmi32b : I2A8 <"and", 0x83, MRMS4m >; // [mem32] &= imm8 + def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>; def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>; def ORrr32 : I2A32<"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>; +def ORmr8 : I2A8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8 +def ORmr16 : I2A16<"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16 +def ORmr32 : I2A32<"or" , 0x09, MRMDestMem>; // [mem32] |= R32 +def ORrm8 : I2A8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8] +def ORrm16 : I2A16<"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16] +def ORrm32 : I2A32<"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32] + def ORri8 : I2A8 <"or" , 0x80, MRMS1r >, Pattern<(set R8 , (or R8 , imm))>; def ORri16 : I2A16<"or" , 0x81, MRMS1r >, OpSize, Pattern<(set R16, (or R16, imm))>; def ORri32 : I2A32<"or" , 0x81, MRMS1r >, Pattern<(set R32, (or R32, imm))>; -def ORri16b : I2A8 <"or" , 0x83, MRMS1r >, OpSize; -def ORri32b : I2A8 <"or" , 0x83, MRMS1r >; +def ORmi8 : I2A8 <"or" , 0x80, MRMS1m >; // [mem8] |= imm8 +def ORmi16 : I2A16<"or" , 0x81, MRMS1m >, OpSize; // [mem16] |= imm16 +def ORmi32 : I2A32<"or" , 0x81, MRMS1m >; // [mem32] |= imm32 + +def ORri16b : I2A8 <"or" , 0x83, MRMS1r >, OpSize; // R16 |= imm8 +def ORri32b : I2A8 <"or" , 0x83, MRMS1r >; // R32 |= imm8 +def ORmi16b : I2A8 <"or" , 0x83, MRMS1m >, OpSize; // [mem16] |= imm8 +def ORmi32b : I2A8 <"or" , 0x83, MRMS1m >; // [mem32] |= imm8 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>; def XORrr16 : I2A16<"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>; def XORrr32 : I2A32<"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>; +def XORmr8 : I2A8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8 +def XORmr16 : I2A16<"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16 +def XORmr32 : I2A32<"xor", 0x31, MRMDestMem>; // [mem32] ^= R32 +def XORrm8 : I2A8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8] +def XORrm16 : I2A16<"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16] +def XORrm32 : I2A32<"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32] + def XORri8 : I2A8 <"xor", 0x80, MRMS6r >, Pattern<(set R8 , (xor R8 , imm))>; def XORri16 : I2A16<"xor", 0x81, MRMS6r >, OpSize, Pattern<(set R16, (xor R16, imm))>; def XORri32 : I2A32<"xor", 0x81, MRMS6r >, Pattern<(set R32, (xor R32, imm))>; -def XORri16b : I2A8 <"xor", 0x83, MRMS6r >, OpSize; -def XORri32b : I2A8 <"xor", 0x83, MRMS6r >; +def XORmi8 : I2A8 <"xor", 0x80, MRMS6m >; // [mem8] ^= R8 +def XORmi16 : I2A16<"xor", 0x81, MRMS6m >, OpSize; // [mem16] ^= R16 +def XORmi32 : I2A32<"xor", 0x81, MRMS6m >; // [mem32] ^= R32 + +def XORri16b : I2A8 <"xor", 0x83, MRMS6r >, OpSize; // R16 ^= imm8 +def XORri32b : I2A8 <"xor", 0x83, MRMS6r >; // R32 ^= imm8 +def XORmi16b : I2A8 <"xor", 0x83, MRMS6m >, OpSize; // [mem16] ^= imm8 +def XORmi32b : I2A8 <"xor", 0x83, MRMS6m >; // [mem32] ^= imm8 // Test instructions are just like AND, except they don't generate a result. def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8 diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp index 3e0af70717c..4d52b74d3fc 100644 --- a/lib/Target/X86/X86PeepholeOpt.cpp +++ b/lib/Target/X86/X86PeepholeOpt.cpp @@ -156,6 +156,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, case X86::ADDmi16: case X86::ADDmi32: case X86::SUBmi16: case X86::SUBmi32: case X86::ANDmi16: case X86::ANDmi32: + case X86::ORmi16: case X86::ORmi32: + case X86::XORmi16: case X86::XORmi32: assert(MI->getNumOperands() == 5 && "These should all have 5 operands!"); if (MI->getOperand(4).isImmediate()) { int Val = MI->getOperand(4).getImmedValue(); @@ -170,6 +172,10 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, case X86::SUBmi32: Opcode = X86::SUBmi32b; break; case X86::ANDmi16: Opcode = X86::ANDmi16b; break; case X86::ANDmi32: Opcode = X86::ANDmi32b; break; + case X86::ORmi16: Opcode = X86::ORmi16b; break; + case X86::ORmi32: Opcode = X86::ORmi32b; break; + case X86::XORmi16: Opcode = X86::XORmi16b; break; + case X86::XORmi32: Opcode = X86::XORmi32b; break; } unsigned R0 = MI->getOperand(0).getReg(); unsigned Scale = MI->getOperand(1).getImmedValue(); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 87d1f918ac8..492aff814db 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -175,6 +175,18 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI, case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break; case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break; case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break; + case X86::ORrr8: NI = MakeMRInst(X86::ORmr8 , FrameIndex, MI); break; + case X86::ORrr16: NI = MakeMRInst(X86::ORmr16, FrameIndex, MI); break; + case X86::ORrr32: NI = MakeMRInst(X86::ORmr32, FrameIndex, MI); break; + case X86::ORri8: NI = MakeMIInst(X86::ORmi8 , FrameIndex, MI); break; + case X86::ORri16: NI = MakeMIInst(X86::ORmi16, FrameIndex, MI); break; + case X86::ORri32: NI = MakeMIInst(X86::ORmi32, FrameIndex, MI); break; + case X86::XORrr8: NI = MakeMRInst(X86::XORmr8 , FrameIndex, MI); break; + case X86::XORrr16: NI = MakeMRInst(X86::XORmr16, FrameIndex, MI); break; + case X86::XORrr32: NI = MakeMRInst(X86::XORmr32, FrameIndex, MI); break; + case X86::XORri8: NI = MakeMIInst(X86::XORmi8 , FrameIndex, MI); break; + case X86::XORri16: NI = MakeMIInst(X86::XORmi16, FrameIndex, MI); break; + case X86::XORri32: NI = MakeMIInst(X86::XORmi32, FrameIndex, MI); break; case X86::CMPrr8: NI = MakeMRInst(X86::CMPmr8 , FrameIndex, MI); break; case X86::CMPrr16: NI = MakeMRInst(X86::CMPmr16, FrameIndex, MI); break; case X86::CMPrr32: NI = MakeMRInst(X86::CMPmr32, FrameIndex, MI); break; @@ -199,6 +211,12 @@ bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI, case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break; case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break; case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break; + case X86::ORrr8: NI = MakeRMInst(X86::ORrm8 , FrameIndex, MI); break; + case X86::ORrr16: NI = MakeRMInst(X86::ORrm16, FrameIndex, MI); break; + case X86::ORrr32: NI = MakeRMInst(X86::ORrm32, FrameIndex, MI); break; + case X86::XORrr8: NI = MakeRMInst(X86::XORrm8 , FrameIndex, MI); break; + case X86::XORrr16: NI = MakeRMInst(X86::XORrm16, FrameIndex, MI); break; + case X86::XORrr32: NI = MakeRMInst(X86::XORrm32, FrameIndex, MI); break; case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break; case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break; case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI);break;