From: Evan Cheng Date: Wed, 15 Nov 2006 20:58:11 +0000 (+0000) Subject: Properly transfer kill / dead info. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6ce7dc2a97260eea5fba414332796464912b9359;p=oota-llvm.git Properly transfer kill / dead info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 6be5e074a39..b3efe056861 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -104,6 +104,7 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, // Make sure this is a reg-reg copy. unsigned Opc = MI->getOpcode(); + MachineInstr *NewMI = NULL; switch(Opc) { default: break; @@ -115,18 +116,20 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned InReg = MI->getOperand(1).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) + NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move unsigned OutReg = MI->getOperand(0).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex) + NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } } break; } + if (NewMI) + NewMI->copyKillDeadInfo(MI); return 0; } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 1eacf4a99d8..d19fc161109 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -147,8 +147,18 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const { // Swap op1/op2 unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); + bool Reg1IsKill = MI->getOperand(1).isKill(); + bool Reg2IsKill = MI->getOperand(2).isKill(); MI->getOperand(2).setReg(Reg1); MI->getOperand(1).setReg(Reg2); + if (Reg1IsKill) + MI->getOperand(2).setIsKill(); + else + MI->getOperand(2).unsetIsKill(); + if (Reg2IsKill) + MI->getOperand(1).setIsKill(); + else + MI->getOperand(1).unsetIsKill(); // Swap the mask around. unsigned MB = MI->getOperand(4).getImmedValue(); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 1a19916a57c..08f51db5af1 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -337,47 +337,51 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because // it takes more than one instruction to store it. unsigned Opc = MI->getOpcode(); - + + MachineInstr *NewMI = NULL; if ((Opc == PPC::OR && MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); - return addFrameReference(BuildMI(TII, PPC::STW, - 3).addReg(InReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::STW, + 3).addReg(InReg), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); - return addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex); } } else if ((Opc == PPC::OR8 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); - return addFrameReference(BuildMI(TII, PPC::STD, - 3).addReg(InReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::STD, + 3).addReg(InReg), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); - return addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex); } } else if (Opc == PPC::FMRD) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); - return addFrameReference(BuildMI(TII, PPC::STFD, - 3).addReg(InReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::STFD, + 3).addReg(InReg), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); - return addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex); } } else if (Opc == PPC::FMRS) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); - return addFrameReference(BuildMI(TII, PPC::STFS, + NewMI = addFrameReference(BuildMI(TII, PPC::STFS, 3).addReg(InReg), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); - return addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex); + NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex); } } - return 0; + + if (NewMI) + NewMI->copyKillDeadInfo(MI); + return NewMI; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index bd2da73c6e7..1eee07058f8 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -77,15 +77,16 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, unsigned OpNum, int FI) const { bool isFloat = false; + MachineInstr *NewMI = NULL; switch (MI->getOpcode()) { case SP::ORrr: if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { if (OpNum == 0) // COPY -> STORE - return BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0) + NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0) .addReg(MI->getOperand(2).getReg()); else // COPY -> LOAD - return BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg()) + NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg()) .addFrameIndex(FI).addImm(0); } break; @@ -94,14 +95,17 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, // FALLTHROUGH case SP::FMOVD: if (OpNum == 0) // COPY -> STORE - return BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3) + NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3) .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg()); else // COPY -> LOAD - return BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2, + NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2, MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0); break; } - return 0; + + if (NewMI) + NewMI->copyKillDeadInfo(MI); + return NewMI; } const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const { diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index ad96c20710d..8a1cb36290a 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -130,6 +130,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { unsigned Dest = MI->getOperand(0).getReg(); unsigned Src = MI->getOperand(1).getReg(); + MachineInstr *NewMI = NULL; switch (MI->getOpcode()) { default: break; case X86::SHUFPSrri: { @@ -140,7 +141,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { unsigned C = MI->getOperand(2).getReg(); unsigned M = MI->getOperand(3).getImmedValue(); if (!Subtarget->hasSSE2() || B != C) return 0; - return BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M); + NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M); + NewMI->copyKillDeadInfo(MI); + return NewMI; } } @@ -157,46 +160,51 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { case X86::INC32r: case X86::INC64_32r: assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1); + NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1); + break; case X86::INC16r: case X86::INC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1); + NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1); + break; case X86::DEC32r: case X86::DEC64_32r: assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1); + NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1); + break; case X86::DEC16r: case X86::DEC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1); + NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1); + break; case X86::ADD32rr: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - return addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src, + NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src, MI->getOperand(2).getReg()); + break; case X86::ADD16rr: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - return addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src, + NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src, MI->getOperand(2).getReg()); + break; case X86::ADD32ri: case X86::ADD32ri8: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - return addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, + NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, MI->getOperand(2).getImmedValue()); - return 0; + break; case X86::ADD16ri: case X86::ADD16ri8: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - return addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, + NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, MI->getOperand(2).getImmedValue()); break; - case X86::SHL16ri: if (DisableLEA16) return 0; case X86::SHL32ri: @@ -208,12 +216,14 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { AM.Scale = 1 << ShAmt; AM.IndexReg = Src; unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; - return addFullAddress(BuildMI(*this, Opc, 5, Dest), AM); + NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM); } break; } - return 0; + if (NewMI) + NewMI->copyKillDeadInfo(MI); + return NewMI; } /// commuteInstruction - We have a few instructions that must be hacked on to @@ -239,7 +249,10 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { unsigned A = MI->getOperand(0).getReg(); unsigned B = MI->getOperand(1).getReg(); unsigned C = MI->getOperand(2).getReg(); - return BuildMI(*this, Opc, 3, A).addReg(C).addReg(B).addImm(Size-Amt); + bool BisKill = MI->getOperand(1).isKill(); + bool CisKill = MI->getOperand(2).isKill(); + return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill) + .addReg(B, false, false, BisKill).addImm(Size-Amt); } default: return TargetInstrInfo::commuteInstruction(MI); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 88c276ee665..353a159d181 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -291,6 +291,7 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, bool isTwoAddr = NumOps > 1 && TII.getOperandConstraint(MI->getOpcode(), 1,TargetInstrInfo::TIED_TO) != -1; + MachineInstr *NewMI = NULL; // Folding a memory location into the two-address part of a two-address // instruction is different than folding it other places. It requires // replacing the *two* registers with the memory location. @@ -465,13 +466,17 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, isTwoAddrFold = true; } else if (i == 0) { // If operand 0 if (MI->getOpcode() == X86::MOV16r0) - return MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI); + NewMI = MakeM0Inst(TII, X86::MOV16mi, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV32r0) - return MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI); + NewMI = MakeM0Inst(TII, X86::MOV32mi, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV64r0) - return MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI); + NewMI = MakeM0Inst(TII, X86::MOV64mi32, FrameIndex, MI); else if (MI->getOpcode() == X86::MOV8r0) - return MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI); + NewMI = MakeM0Inst(TII, X86::MOV8mi, FrameIndex, MI); + if (NewMI) { + NewMI->copyKillDeadInfo(MI); + return NewMI; + } static const TableEntry OpcodeTable[] = { { X86::CMP16ri, X86::CMP16mi }, @@ -828,9 +833,11 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI, if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize, fromOpcode)) { if (isTwoAddrFold) - return FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII); - - return FuseInst(Entry->to, i, FrameIndex, MI, TII); + NewMI = FuseTwoAddrInst(Entry->to, FrameIndex, MI, TII); + else + NewMI = FuseInst(Entry->to, i, FrameIndex, MI, TII); + NewMI->copyKillDeadInfo(MI); + return NewMI; } }