From: Nadav Rotem <nadav.rotem@intel.com>
Date: Tue, 16 Aug 2011 14:34:29 +0000 (+0000)
Subject: Revert r137562 because it caused PR10674
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6d1f5d951bab2222096210e76e6f7e18e88ae547;p=oota-llvm.git

Revert r137562 because it caused PR10674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137719 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index ab6af1b4d17..8b353a28b6b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -928,13 +928,6 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
   assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
          "APInt size does not match type size!");
 
-  // In some cases the vector type is legal but the element type is illegal.
-  // In this case, promote the inserted value. The type does not need to match
-  // the vector element type. Any extra bits introduced will be
-  // truncated away.
-  if (VT.isVector())
-    EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
-
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);