From: Vikram S. Adve Date: Wed, 10 Oct 2001 20:58:11 +0000 (+0000) Subject: Don't insert useful instructions in delay slot of a RETURN. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6db77c55ff6c591739b41a5a5666c304405952f0;p=oota-llvm.git Don't insert useful instructions in delay slot of a RETURN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@721 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 0b194207ca4..79c89410355 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -1258,9 +1258,11 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S, // is found for a delay slot, use the NOP that is currently in that slot. // // We try to fill the delay slots with useful work for all instructions -// except CALLs. For CALLs, it is nearly always possible to use one of the +// EXCEPT CALLS AND RETURNS. +// For CALLs and RETURNs, it is nearly always possible to use one of the // call sequence instrs and putting anything else in the delay slot could be -// suboptimal. +// suboptimal. Also, it complicates generating the calling sequence code in +// regalloc. // static void ChooseInstructionsForDelaySlots(SchedulingManager& S, @@ -1271,35 +1273,38 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, const TerminatorInst* termInstr = bb->getTerminator(); MachineCodeForVMInstr& termMvec = termInstr->getMachineInstrVec(); vector delayNodeVec; - const MachineInstr* brInstr; + const MachineInstr* brInstr = NULL; assert(termInstr->getOpcode() != Instruction::Call && "Call used as terminator?"); - // To find instructions that need delay slots without searching the entire - // machine code, we assume the only delayed instructions are CALLs or - // instructions generated for the terminator inst. - // Find the first branch instr in the sequence of machine instrs for term - // - unsigned first = 0; - while (first < termMvec.size() && - ! mii.isBranch(termMvec[first]->getOpCode())) + if (termInstr->getOpcode() != Instruction::Ret) { - ++first; - } - assert(first < termMvec.size() && - "No branch instructions for BR? Ok, but weird! Delete assertion."); - - brInstr = (first < termMvec.size())? termMvec[first] : NULL; - - // Compute a vector of the nodes chosen for delay slots and then - // mark delay slots to replace NOPs with these useful instructions. - // - if (brInstr != NULL) - { - SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr); - FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec); - ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph); + // To find instructions that need delay slots without searching the full + // machine code, we assume that the only delayed instructions are CALLs + // or instructions generated for the terminator inst. + // Find the first branch instr in the sequence of machine instrs for term + // + unsigned first = 0; + while (first < termMvec.size() && + ! mii.isBranch(termMvec[first]->getOpCode())) + { + ++first; + } + assert(first < termMvec.size() && + "No branch instructions for BR? Ok, but weird! Delete assertion."); + + brInstr = (first < termMvec.size())? termMvec[first] : NULL; + + // Compute a vector of the nodes chosen for delay slots and then + // mark delay slots to replace NOPs with these useful instructions. + // + if (brInstr != NULL) + { + SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr); + FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec); + ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph); + } } // Also mark delay slots for other delayed instructions to hold NOPs. diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index fd09e9e7778..97a3b7ab4cc 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -632,7 +632,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr, // machine instruction in the instruction sequence for this VM instr // (at least for now, there is never more than one machine instr). // - const vector& implicitUses = + const vector& implicitUses = instr.getMachineInstrVec().getImplicitUses(); for (unsigned i=0; i < implicitUses.size(); ++i) addSSAEdge(node, implicitUses[i], target); diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 0b194207ca4..79c89410355 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -1258,9 +1258,11 @@ ReplaceNopsWithUsefulInstr(SchedulingManager& S, // is found for a delay slot, use the NOP that is currently in that slot. // // We try to fill the delay slots with useful work for all instructions -// except CALLs. For CALLs, it is nearly always possible to use one of the +// EXCEPT CALLS AND RETURNS. +// For CALLs and RETURNs, it is nearly always possible to use one of the // call sequence instrs and putting anything else in the delay slot could be -// suboptimal. +// suboptimal. Also, it complicates generating the calling sequence code in +// regalloc. // static void ChooseInstructionsForDelaySlots(SchedulingManager& S, @@ -1271,35 +1273,38 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, const TerminatorInst* termInstr = bb->getTerminator(); MachineCodeForVMInstr& termMvec = termInstr->getMachineInstrVec(); vector delayNodeVec; - const MachineInstr* brInstr; + const MachineInstr* brInstr = NULL; assert(termInstr->getOpcode() != Instruction::Call && "Call used as terminator?"); - // To find instructions that need delay slots without searching the entire - // machine code, we assume the only delayed instructions are CALLs or - // instructions generated for the terminator inst. - // Find the first branch instr in the sequence of machine instrs for term - // - unsigned first = 0; - while (first < termMvec.size() && - ! mii.isBranch(termMvec[first]->getOpCode())) + if (termInstr->getOpcode() != Instruction::Ret) { - ++first; - } - assert(first < termMvec.size() && - "No branch instructions for BR? Ok, but weird! Delete assertion."); - - brInstr = (first < termMvec.size())? termMvec[first] : NULL; - - // Compute a vector of the nodes chosen for delay slots and then - // mark delay slots to replace NOPs with these useful instructions. - // - if (brInstr != NULL) - { - SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr); - FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec); - ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph); + // To find instructions that need delay slots without searching the full + // machine code, we assume that the only delayed instructions are CALLs + // or instructions generated for the terminator inst. + // Find the first branch instr in the sequence of machine instrs for term + // + unsigned first = 0; + while (first < termMvec.size() && + ! mii.isBranch(termMvec[first]->getOpCode())) + { + ++first; + } + assert(first < termMvec.size() && + "No branch instructions for BR? Ok, but weird! Delete assertion."); + + brInstr = (first < termMvec.size())? termMvec[first] : NULL; + + // Compute a vector of the nodes chosen for delay slots and then + // mark delay slots to replace NOPs with these useful instructions. + // + if (brInstr != NULL) + { + SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr); + FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec); + ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph); + } } // Also mark delay slots for other delayed instructions to hold NOPs. diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index fd09e9e7778..97a3b7ab4cc 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -632,7 +632,7 @@ SchedGraph::addEdgesForInstruction(const MachineInstr& minstr, // machine instruction in the instruction sequence for this VM instr // (at least for now, there is never more than one machine instr). // - const vector& implicitUses = + const vector& implicitUses = instr.getMachineInstrVec().getImplicitUses(); for (unsigned i=0; i < implicitUses.size(); ++i) addSSAEdge(node, implicitUses[i], target);