From: Jim Grosbach Date: Mon, 22 Aug 2011 23:17:34 +0000 (+0000) Subject: Improve error checking for tPUSH and tPOP register lists. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6dcafc0d0b33bebcac28539257a9a5b250542f6a;p=oota-llvm.git Improve error checking for tPUSH and tPOP register lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 0632e85d361..1ca3e1d120b 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3109,6 +3109,26 @@ validateInstruction(MCInst &Inst, break; } + case ARM::tPOP: { + for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { + unsigned Reg = Inst.getOperand(i).getReg(); + // Anything other than a low register isn't legal here. + if (!isARMLowRegister(Reg) && Reg != ARM::PC) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or pc"); + } + break; + } + case ARM::tPUSH: { + for (unsigned i = 2; i < Inst.getNumOperands(); ++i) { + unsigned Reg = Inst.getOperand(i).getReg(); + // Anything other than a low register isn't legal here. + if (!isARMLowRegister(Reg) && Reg != ARM::LR) + return Error(Operands[2]->getStartLoc(), + "registers must be in range r0-r7 or lr"); + } + break; + } } return false; diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index 1c7db6323b5..55b062e3993 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -57,6 +57,18 @@ error: invalid operand for instruction @ CHECK-ERRORS: ^ +@ Invalid writeback and register lists for PUSH/POP + pop {r1, r2, r10} + push {r8, r9} +@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc +@ CHECK-ERRORS: pop {r1, r2, r10} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr +@ CHECK-ERRORS: push {r8, r9} +@ CHECK-ERRORS: ^ + + + @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 lsls r4, r5, #32