From: ling.ma@intel.com <ling.ma@intel.com>
Date: Thu, 25 Jun 2009 02:59:22 +0000 (+0800)
Subject: drm/i915: Set SSC frequency for 8xx chips correctly
X-Git-Tag: firefly_0821_release~13431^2~19
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=6ff4fd05676bc5b5c930bef25901e489f7843660;p=firefly-linux-kernel-4.4.55.git

drm/i915: Set SSC frequency for 8xx chips correctly

All 8xx class chips have the 66/48 split, not just 855.

Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
---

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 716409a57244..da22863c05c0 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
 		dev_priv->lvds_use_ssc = general->enable_ssc;
 
 		if (dev_priv->lvds_use_ssc) {
-		  if (IS_I855(dev_priv->dev))
-		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
-		  else
-		    dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
+			if (IS_I85X(dev_priv->dev))
+				dev_priv->lvds_ssc_freq =
+					general->ssc_freq ? 66 : 48;
+			else
+				dev_priv->lvds_ssc_freq =
+					general->ssc_freq ? 100 : 96;
 		}
 	}
 }