From: Chris Lattner Date: Tue, 21 Sep 2010 19:41:58 +0000 (+0000) Subject: even though I'm about to rip it out, simplify the address mode stuff X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=701cd622978ffe8c3197c0c465b97c5f2aeb8346;p=oota-llvm.git even though I'm about to rip it out, simplify the address mode stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114468 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 0c3c7734e39..da2a525e4a8 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -404,10 +404,8 @@ static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) { return false; // FIXME: Calls can't fold loads through segment registers yet. - if (const Value *Src = LD->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - if (PT->getAddressSpace() >= 256) - return false; + if (LD->getPointerInfo().getAddrSpace() > 255) + return false; // Now let's find the callseq_start. while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) { diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 8db1dc76de4..ac661dc7bd4 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -421,25 +421,17 @@ def i32immSExt8 : PatLeaf<(i32 immSext8)>; /// Load patterns: these constraint the match to the right address space. def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - if (const Value *Src = cast(N)->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - if (PT->getAddressSpace() > 255) - return false; + if (cast(N)->getPointerInfo().getAddrSpace() > 255) + return false; return true; }]>; def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - if (const Value *Src = cast(N)->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - return PT->getAddressSpace() == 256; - return false; + return cast(N)->getPointerInfo().getAddrSpace() == 256; }]>; def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - if (const Value *Src = cast(N)->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - return PT->getAddressSpace() == 257; - return false; + return cast(N)->getPointerInfo().getAddrSpace() == 257; }]>; @@ -448,10 +440,9 @@ def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ // known to be 32-bit aligned or better. Ditto for i8 to i16. def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ LoadSDNode *LD = cast(N); - if (const Value *Src = LD->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - if (PT->getAddressSpace() > 255) - return false; + if (LD->getPointerInfo().getAddrSpace() > 255) + return false; + ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) return true; @@ -462,10 +453,8 @@ def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ LoadSDNode *LD = cast(N); - if (const Value *Src = LD->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - if (PT->getAddressSpace() > 255) - return false; + if (LD->getPointerInfo().getAddrSpace() > 255) + return false; ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::EXTLOAD) return LD->getAlignment() >= 2 && !LD->isVolatile(); @@ -474,10 +463,8 @@ def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ LoadSDNode *LD = cast(N); - if (const Value *Src = LD->getSrcValue()) - if (const PointerType *PT = dyn_cast(Src->getType())) - if (PT->getAddressSpace() > 255) - return false; + if (LD->getPointerInfo().getAddrSpace() > 255) + return false; ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) return true;