From: Ken Dyck <ken.dyck@onsemi.com>
Date: Thu, 17 Dec 2009 15:31:52 +0000 (+0000)
Subject: In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=70d0ef1459f332cb7944a20ed65dac3637a2aca7;p=oota-llvm.git

In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of
incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91602 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index aa6967ab43b..fb5b4ccd413 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4584,7 +4584,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
                                                  MVT::v4i32, Vec),
                                      Op.getOperand(1)));
     // Transform it so it match pextrw which produces a 32-bit result.
-    EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
+    EVT EltVT = MVT::i32;
     SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
                                     Op.getOperand(0), Op.getOperand(1));
     SDValue Assert  = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,