From: dkl <dkl@rock-chips.com>
Date: Wed, 17 Dec 2014 08:36:17 +0000 (+0800)
Subject: clk: rockchip: set aclk_core_div to 4 for all rates in rk3036_apll_table
X-Git-Tag: firefly_0821_release~4366
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=72dca47db44009a46ade2691ecc853c3600449f9;p=firefly-linux-kernel-4.4.55.git

clk: rockchip: set aclk_core_div to 4 for all rates in rk3036_apll_table

Set aclk_core_div to 4 for all rates, which makes rk3126\rk3128\rk3126b apll
frequency change stably.

Signed-off-by: dkl <dkl@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index cdba78589c4c..6786f7fe2f85 100755
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -191,7 +191,7 @@ static const struct apll_clk_set rk3036_apll_table[] = {
 	_RK3036_APLL_SET_CLKS(1368, 1, 57, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(1344, 1, 56, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(1320, 1, 55, 1, 1, 1, 0, 81, 41, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81, 81, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(1296, 1, 54, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(1272, 1, 53, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(1248, 1, 52, 1, 1, 1, 0, 81, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(1200, 1, 50, 1, 1, 1, 0, 81, 41, 41, 21, 21),
@@ -211,14 +211,14 @@ static const struct apll_clk_set rk3036_apll_table[] = {
 	_RK3036_APLL_SET_CLKS(800, 6, 400, 2, 1, 1, 0, 41, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(700, 6, 350, 2, 1, 1, 0, 41, 41, 41, 21, 21),
 	_RK3036_APLL_SET_CLKS(696, 1, 58, 2, 1, 1, 0, 41, 41, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21, 21, 41, 21, 21),
-	_RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21, 21, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(600, 1, 75, 3, 1, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(504, 1, 63, 3, 1, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(500, 6, 250, 2, 1, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(408, 1, 68, 2, 2, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(312, 1, 52, 2, 2, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(216, 1, 72, 4, 2, 1, 0, 41, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(96, 1, 64, 4, 4, 1, 0, 21, 41, 41, 21, 21),
+	_RK3036_APLL_SET_CLKS(0, 1, 0, 1, 1, 1, 0, 21, 41, 41, 21, 21),
 };
 
 static const struct pll_clk_set rk3036plus_pll_com_table[] = {