From: Evgeniy Stepanov Date: Thu, 19 Jan 2012 12:53:06 +0000 (+0000) Subject: Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=73dd8bbce3ff54c318233027fb5e29f8298e01d6;p=oota-llvm.git Emit ARM EHABI unwinding instructions for 3 more Thumb instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index e38485318aa..85959fea374 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1107,6 +1107,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { break; case ARM::STR_PRE_IMM: case ARM::STR_PRE_REG: + case ARM::t2STR_PRE: assert(MI->getOperand(2).getReg() == ARM::SP && "Only stack pointer as a source reg is supported"); RegList.push_back(SrcReg); @@ -1122,12 +1123,14 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { MI->dump(); assert(0 && "Unsupported opcode for unwinding information"); case ARM::MOVr: + case ARM::tMOVr: Offset = 0; break; case ARM::ADDri: Offset = -MI->getOperand(2).getImm(); break; case ARM::SUBri: + case ARM::t2SUBri: Offset = MI->getOperand(2).getImm(); break; case ARM::tSUBspi: diff --git a/test/CodeGen/ARM/ehabi-unwind.ll b/test/CodeGen/ARM/ehabi-unwind.ll new file mode 100644 index 00000000000..1ffde00365a --- /dev/null +++ b/test/CodeGen/ARM/ehabi-unwind.ll @@ -0,0 +1,15 @@ +; Test that the EHABI unwind instruction generator does not encounter any +; unfamiliar instructions. +; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi -disable-fp-elim +; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi + +define void @_Z1fv() nounwind { +entry: + ret void +} + +define void @_Z1gv() nounwind { +entry: + call void @_Z1fv() + ret void +}