From: Douglas Katzman Date: Wed, 19 Aug 2015 19:30:57 +0000 (+0000) Subject: [Sparc]: asm-only support for the ldstub instruction. X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=73e587e7f990867e31604f93b04913c7bf0fabc8;p=oota-llvm.git [Sparc]: asm-only support for the ldstub instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245485 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 21e9f70e4db..5da4983eab4 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -298,6 +298,17 @@ multiclass LoadA Op3Val, bits<6> LoadAOp3Val, def Arr : LoadASI; } +// The LDSTUB instruction is supported for asm only. +// It is unlikely that general-purpose code could make use of it. +// CAS is preferred for sparc v9. +def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), + "ldstub [$addr], $dst", []>; +def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), + "ldstub [$addr], $dst", []>; +def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), + (ins MEMrr:$addr, i8imm:$asi), + "ldstuba [$addr] $asi, $dst", []>; + // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> { diff --git a/test/MC/Sparc/sparc-atomic-instructions.s b/test/MC/Sparc/sparc-atomic-instructions.s index 17f97d4b535..4ce19d5cdda 100644 --- a/test/MC/Sparc/sparc-atomic-instructions.s +++ b/test/MC/Sparc/sparc-atomic-instructions.s @@ -12,3 +12,12 @@ ! CHECK: swapa [%i0+%l6] 131, %o2 ! encoding: [0xd4,0xfe,0x10,0x76] swapa [%i0+%l6] 131, %o2 + + ! CHECK: ldstub [%i0+40], %g1 ! encoding: [0xc2,0x6e,0x20,0x28] + ldstub [%i0+40], %g1 + + ! CHECK: ldstub [%i0+%i2], %g1 ! encoding: [0xc2,0x6e,0x00,0x1a] + ldstub [%i0+%i2], %g1 + + ! CHECK: ldstuba [%i0+%i2] 131, %g1 ! encoding: [0xc2,0xee,0x10,0x7a] + ldstuba [%i0+%i2] 131, %g1