From: Benjamin Kramer <benny.kra@googlemail.com>
Date: Thu, 22 Sep 2011 03:01:42 +0000 (+0000)
Subject: X86: Don't form min/max nodes if the target is missing SSE.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=74f3501d15c05a92eeb7962da76e97cabc3c7557;p=oota-llvm.git

X86: Don't form min/max nodes if the target is missing SSE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140294 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 36e254b1f58..996dd12d3e4 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -12568,7 +12568,8 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
   // instructions match the semantics of the common C idiom x<y?x:y but not
   // x<=y?x:y, because of how they handle negative zero (which can be
   // ignored in unsafe-math mode).
-  if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
+  if (Subtarget->hasXMM() &&
+      Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
       VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();