From: Daniel Sanders Date: Thu, 3 Apr 2014 14:14:22 +0000 (+0000) Subject: [mips] Add negative tests confirm that supported ISA's don't allow instructions added... X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=769a6f211604f0285c419102846cfc91ab1e63cc;p=oota-llvm.git [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's Summary: test/MC/Mips//invalid-.s Test that does not support 's instructions. test/MC/Mips//invalid--xfail.s Things that should be invalid but currently aren't. Will XPASS if any become invalid. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3262 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205538 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/MC/Mips/mips32/invalid-mips32r2-xfail.s b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s new file mode 100644 index 00000000000..73fba94de59 --- /dev/null +++ b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s @@ -0,0 +1,19 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + di $s8 + ei $t6 + luxc1 $f19,$s6($s5) + mfhc1 $s8,$f24 + mthc1 $zero,$f16 + rdhwr $sp,$11 + suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips32/invalid-mips32r2.s b/test/MC/Mips/mips32/invalid-mips32r2.s index b400eea6917..881f7f11e75 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2.s +++ b/test/MC/Mips/mips32/invalid-mips32r2.s @@ -5,4 +5,19 @@ # RUN: FileCheck %s < %t1 .set noat - pause # CHECK: requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index b42005537f4..3e9a1d37452 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -89,6 +89,7 @@ msub.d $f10,$f1,$f31,$f18 msub.s $f12,$f19,$f10,$f16 msubu $t7,$a1 + mtc0 $t1,$29,3 mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1 diff --git a/test/MC/Mips/mips4/invalid-mips64-xfail.s b/test/MC/Mips/mips4/invalid-mips64-xfail.s new file mode 100644 index 00000000000..d8ebcd3e2cc --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips64-xfail.s @@ -0,0 +1,22 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + deret + luxc1 $f19,$s6($s5) + madd $s6,$t5 + madd $zero,$t1 + maddu $s3,$gp + maddu $t8,$s2 + mfc0 $a2,$14,1 + msub $s7,$k1 + msubu $t7,$a1 + mtc0 $t1,$29,3 + mul $s0,$s4,$at + suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips4/invalid-mips64.s b/test/MC/Mips/mips4/invalid-mips64.s new file mode 100644 index 00000000000..e0b69f21081 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips64.s @@ -0,0 +1,12 @@ +# Instructions that are invalid +# +# FIXME: This test should be moved to the mips5 directory when mips5 is supported +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64r2-xfail.s b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s new file mode 100644 index 00000000000..63edb6009bb --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s @@ -0,0 +1,27 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + deret + di $s8 + ei $t6 + luxc1 $f19,$s6($s5) + madd $s6,$t5 + madd $zero,$t1 + maddu $s3,$gp + maddu $t8,$s2 + mfc0 $a2,$14,1 + mfhc1 $s8,$f24 + msub $s7,$k1 + msubu $t7,$a1 + mtc0 $t1,$29,3 + mthc1 $zero,$f16 + mul $s0,$s4,$at + rdhwr $sp,$11 + suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips4/invalid-mips64r2.s b/test/MC/Mips/mips4/invalid-mips64r2.s new file mode 100644 index 00000000000..ed2dff83c6b --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips64r2.s @@ -0,0 +1,22 @@ +# Instructions that are invalid +# +# FIXME: This test should be moved to the mips5 directory when mips5 is supported +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64/invalid-mips64r2-xfail.s b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s new file mode 100644 index 00000000000..4baf26bc1d2 --- /dev/null +++ b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s @@ -0,0 +1,15 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + di $s8 + ei $t6 + mfhc1 $s8,$f24 + mthc1 $zero,$f16 + rdhwr $sp,$11 diff --git a/test/MC/Mips/mips64/invalid-mips64r2.s b/test/MC/Mips/mips64/invalid-mips64r2.s index 5e687d0a1b7..41aa8ae4798 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2.s +++ b/test/MC/Mips/mips64/invalid-mips64r2.s @@ -4,5 +4,14 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat - pause # CHECK: requires a CPU feature not currently enabled + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 34771b9afd3..826a6b2e60b 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -118,6 +118,7 @@ msub $s7,$k1 msub.s $f12,$f19,$f10,$f16 msubu $t7,$a1 + mtc0 $t1,$29,3 mtc1 $s8,$f9 mthc1 $zero,$f16 mthi $s1