From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 18 Feb 2015 02:10:40 +0000 (+0000)
Subject: R600/SI: Fix encoding error from glc bit on VI SMRD instructions
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=76f78b9ac2c135d16de28a196c85db335bbb7d22;p=oota-llvm.git

R600/SI: Fix encoding error from glc bit on VI SMRD instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229608 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 520379225d9..3443d4ba9ee 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -576,7 +576,11 @@ multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
 
   def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
 
-  def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
+  // glc is only applicable to scalar stores, which are not yet
+  // implemented.
+  let glc = 0 in {
+    def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
+  }
 }
 
 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,