From: Yoshinori Sato Date: Thu, 7 Dec 2006 09:01:23 +0000 (+0900) Subject: sh: IPR IRQ updates for SH7619/SH7206. X-Git-Tag: firefly_0821_release~31885^2~5^2~19 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=780a1568886a2f5df9bf11b72ba0624c80db5b3b;p=firefly-linux-kernel-4.4.55.git sh: IPR IRQ updates for SH7619/SH7206. This updates the SH7619 and SH7206 code for the IPR IRQ changes. Signed-off-by: Yoshinori Sato Signed-off-by: Paul Mundt --- diff --git a/arch/sh/boards/se/7206/irq.c b/arch/sh/boards/se/7206/irq.c index 3fb0c5f5b23a..27da88486f73 100644 --- a/arch/sh/boards/se/7206/irq.c +++ b/arch/sh/boards/se/7206/irq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #define INTSTS0 0x31800000 @@ -18,6 +19,13 @@ #define INTMSK1 0x31800006 #define INTSEL 0x31800008 +#define IRQ0_IRQ 64 +#define IRQ1_IRQ 65 +#define IRQ3_IRQ 67 + +#define INTC_IPR01 0xfffe0818 +#define INTC_ICR1 0xfffe0802 + static void disable_se7206_irq(unsigned int irq) { unsigned short val; @@ -39,7 +47,7 @@ static void disable_se7206_irq(unsigned int irq) case IRQ1_IRQ: msk0 |= 0x000f; break; - case IRQ2_IRQ: + case IRQ3_IRQ: msk0 |= 0x0f00; msk1 |= 0x00ff; break; @@ -70,7 +78,7 @@ static void enable_se7206_irq(unsigned int irq) case IRQ1_IRQ: msk0 &= ~0x000f; break; - case IRQ2_IRQ: + case IRQ3_IRQ: msk0 &= ~0x0f00; msk1 &= ~0x00ff; break; @@ -96,7 +104,7 @@ static void eoi_se7206_irq(unsigned int irq) case IRQ1_IRQ: sts0 &= ~0x000f; break; - case IRQ2_IRQ: + case IRQ3_IRQ: sts0 &= ~0x0f00; sts1 &= ~0x00ff; break; @@ -106,7 +114,7 @@ static void eoi_se7206_irq(unsigned int irq) } static struct irq_chip se7206_irq_chip __read_mostly = { - .name = "SE7206-FPGA-IRQ", + .name = "SE7206-FPGA", .mask = disable_se7206_irq, .unmask = enable_se7206_irq, .mask_ack = disable_se7206_irq, diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 82c2d905152f..79283e6c1d8f 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c @@ -51,3 +51,44 @@ static int __init sh7619_devices_setup(void) ARRAY_SIZE(sh7619_devices)); } __initcall(sh7619_devices_setup); + +#define INTC_IPRC 0xf8080000UL +#define INTC_IPRD 0xf8080002UL + +#define CMI0_IRQ 86 + +#define SCIF0_ERI_IRQ 88 +#define SCIF0_RXI_IRQ 89 +#define SCIF0_BRI_IRQ 90 +#define SCIF0_TXI_IRQ 91 + +#define SCIF1_ERI_IRQ 92 +#define SCIF1_RXI_IRQ 93 +#define SCIF1_BRI_IRQ 94 +#define SCIF1_TXI_IRQ 95 + +#define SCIF2_BRI_IRQ 96 +#define SCIF2_ERI_IRQ 97 +#define SCIF2_RXI_IRQ 98 +#define SCIF2_TXI_IRQ 99 + +static struct ipr_data sh7619_ipr_map[] = { + { CMI0_IRQ, INTC_IPRC, 1, 2 }, + { SCIF0_ERI_IRQ, INTC_IPRD, 3, 3 }, + { SCIF0_RXI_IRQ, INTC_IPRD, 3, 3 }, + { SCIF0_BRI_IRQ, INTC_IPRD, 3, 3 }, + { SCIF0_TXI_IRQ, INTC_IPRD, 3, 3 }, + { SCIF1_ERI_IRQ, INTC_IPRD, 2, 3 }, + { SCIF1_RXI_IRQ, INTC_IPRD, 2, 3 }, + { SCIF1_BRI_IRQ, INTC_IPRD, 2, 3 }, + { SCIF1_TXI_IRQ, INTC_IPRD, 2, 3 }, + { SCIF2_ERI_IRQ, INTC_IPRD, 1, 3 }, + { SCIF2_RXI_IRQ, INTC_IPRD, 1, 3 }, + { SCIF2_BRI_IRQ, INTC_IPRD, 1, 3 }, + { SCIF2_TXI_IRQ, INTC_IPRD, 1, 3 }, +}; + +void __init init_IRQ_ipr(void) +{ + make_ipr_irq(sh7619_ipr_map, ARRAY_SIZE(sh7619_ipr_map)); +} diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index cdfeef49e62e..4b60fcc7d667 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c @@ -17,22 +17,22 @@ static struct plat_sci_port sci_platform_data[] = { .mapbase = 0xfffe8000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 240, 241, 242, 243}, + .irqs = { 241, 242, 243, 240}, }, { .mapbase = 0xfffe8800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 244, 245, 246, 247}, + .irqs = { 247, 244, 245, 246}, }, { .mapbase = 0xfffe9000, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 248, 249, 250, 251}, + .irqs = { 249, 250, 251, 248}, }, { .mapbase = 0xfffe9800, .flags = UPF_BOOT_AUTOCONF, .type = PORT_SCIF, - .irqs = { 252, 253, 254, 255}, + .irqs = { 253, 254, 255, 252}, }, { .flags = 0, } @@ -56,3 +56,57 @@ static int __init sh7206_devices_setup(void) ARRAY_SIZE(sh7206_devices)); } __initcall(sh7206_devices_setup); + +#define INTC_IPR08 0xfffe0c04UL +#define INTC_IPR09 0xfffe0c06UL +#define INTC_IPR14 0xfffe0c10UL + +#define CMI0_IRQ 140 + +#define MTU1_TGI1A 164 + +#define SCIF0_BRI_IRQ 240 +#define SCIF0_ERI_IRQ 241 +#define SCIF0_RXI_IRQ 242 +#define SCIF0_TXI_IRQ 243 + +#define SCIF1_BRI_IRQ 244 +#define SCIF1_ERI_IRQ 245 +#define SCIF1_RXI_IRQ 246 +#define SCIF1_TXI_IRQ 247 + +#define SCIF2_BRI_IRQ 248 +#define SCIF2_ERI_IRQ 249 +#define SCIF2_RXI_IRQ 250 +#define SCIF2_TXI_IRQ 251 + +#define SCIF3_BRI_IRQ 252 +#define SCIF3_ERI_IRQ 253 +#define SCIF3_RXI_IRQ 254 +#define SCIF3_TXI_IRQ 255 + +static struct ipr_data sh7206_ipr_map[] = { + { CMI0_IRQ, INTC_IPR08, 3, 2 }, + { MTU2_TGI1A, INTC_IPR09, 1, 2 }, + { SCIF0_ERI_IRQ, INTC_IPR14, 3, 3 }, + { SCIF0_RXI_IRQ, INTC_IPR14, 3, 3 }, + { SCIF0_BRI_IRQ, INTC_IPR14, 3, 3 }, + { SCIF0_TXI_IRQ, INTC_IPR14, 3, 3 }, + { SCIF1_ERI_IRQ, INTC_IPR14, 2, 3 }, + { SCIF1_RXI_IRQ, INTC_IPR14, 2, 3 }, + { SCIF1_BRI_IRQ, INTC_IPR14, 2, 3 }, + { SCIF1_TXI_IRQ, INTC_IPR14, 2, 3 }, + { SCIF2_ERI_IRQ, INTC_IPR14, 1, 3 }, + { SCIF2_RXI_IRQ, INTC_IPR14, 1, 3 }, + { SCIF2_BRI_IRQ, INTC_IPR14, 1, 3 }, + { SCIF2_TXI_IRQ, INTC_IPR14, 1, 3 }, + { SCIF3_ERI_IRQ, INTC_IPR14, 0, 3 }, + { SCIF3_RXI_IRQ, INTC_IPR14, 0, 3 }, + { SCIF3_BRI_IRQ, INTC_IPR14, 0, 3 }, + { SCIF3_TXI_IRQ, INTC_IPR14, 0, 3 }, +}; + +void __init init_IRQ_ipr(void) +{ + make_ipr_irq(sh7206_ipr_map, ARRAY_SIZE(sh7206_ipr_map)); +}