From: 陈亮 Date: Thu, 17 Jul 2014 06:27:27 +0000 (-0700) Subject: ARM: rockchip: rk312x: add initial support X-Git-Tag: firefly_0821_release~4916^2~219 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=780b2b158c0e1e911b10683e3e56f0ca8240b9d8;p=firefly-linux-kernel-4.4.55.git ARM: rockchip: rk312x: add initial support --- diff --git a/arch/arm/boot/dts/rk3126-fpga.dts b/arch/arm/boot/dts/rk3126-fpga.dts new file mode 100644 index 000000000000..e832e0a76263 --- /dev/null +++ b/arch/arm/boot/dts/rk3126-fpga.dts @@ -0,0 +1,19 @@ +/dts-v1/; +#include "rk312x.dtsi" + +/ { + compatible = "rockchip,rk312x"; + + memory { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; + + chosen { + bootargs = "androidboot.console=ttyFIQ0 initrd=0x62000000,0x00800000"; + }; + + fiq-debugger { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/rk3126-sdk.dts b/arch/arm/boot/dts/rk3126-sdk.dts new file mode 100644 index 000000000000..f4f93a41557b --- /dev/null +++ b/arch/arm/boot/dts/rk3126-sdk.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "rk3288.dtsi" +#include "lcd-b101ew05.dtsi" + +/ { + fiq-debugger { + status = "okay"; + }; + }; diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi new file mode 100755 index 000000000000..ca328988dffa --- /dev/null +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -0,0 +1,102 @@ +#include +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "rockchip,rk312x"; + rockchip,sram = <&sram>; + interrupt-parent = <&gic>; + + aliases { + /* serial0 = &uart_bt; + serial1 = &uart_bb;*/ + serial2 = &uart2;/* + serial3 = &uart_gps; + serial4 = &uart_exp; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + lcdc0 = &lcdc0; + lcdc1 = &lcdc1; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2;*/ + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + map-exec; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + ; + clock-frequency = <24000000>; + }; + + uart2: serial@20068000 { + compatible = "rockchip,serial"; + reg = <0x20068000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + //clocks = <&clk_uart2>, <&clk_gates11 9>; + //clock-names = "sclk_uart", "pclk_uart"; + reg-shift = <2>; + reg-io-width = <4>; + // dmas = <&pdma0 4>, <&pdma0 5>; + #dma-cells = <2>; + // pinctrl-names = "default"; + // pinctrl-0 = <&uart2_xfer>; + status = "disabled"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <106>; + rockchip,wake-irq = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 57964d66dec0..5f47f27804b6 100755 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -1,6 +1,7 @@ obj-y += common.o obj-y += cpu.o obj-y += rk3036.o +obj-y += rk312x.o obj-y += rk3188.o obj-y += rk3288.o obj-y += ddr_freq.o diff --git a/arch/arm/mach-rockchip/rk312x.c b/arch/arm/mach-rockchip/rk312x.c new file mode 100755 index 000000000000..b7f244843930 --- /dev/null +++ b/arch/arm/mach-rockchip/rk312x.c @@ -0,0 +1,106 @@ +/* + * Device Tree support for Rockchip RK3288 + * + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cpu_axi.h" +#include "loader.h" +#define CPU 312X +#include "sram.h" +#include "pm.h" + +#define RK312x_DEVICE(name) \ + { \ + .virtual = (unsigned long) RK_##name##_VIRT, \ + .pfn = __phys_to_pfn(RK312X_##name##_PHYS), \ + .length = RK312X_##name##_SIZE, \ + .type = MT_DEVICE, \ + } + +static const char * const rk312x_dt_compat[] __initconst = { + "rockchip,rk312x", + NULL, +}; + +static struct map_desc rk312x_io_desc[] __initdata = { + RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE), + RK312x_DEVICE(TIMER), +}; + +#define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0) + +static void __init rk312x_dt_map_io(void) +{ + rockchip_soc_id = ROCKCHIP_SOC_RK3126; + + iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc)); + debug_ll_io_init(); + + /* enable timer5 for core */ + writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10); + dsb(); + writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00); + writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04); + dsb(); + writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10); + dsb(); +} + +static void __init rk312x_dt_init_timer(void) +{ + clocksource_of_init(); +} + +static void __init rk312x_reserve(void) +{ +} + +static void __init rk312x_init_late(void) +{ +} + +static void rk312x_restart(char mode, const char *cmd) +{ +} + +DT_MACHINE_START(RK312X_DT, "Rockchip RK312X") + .smp = smp_ops(rockchip_smp_ops), + .map_io = rk312x_dt_map_io, + .init_time = rk312x_dt_init_timer, + .dt_compat = rk312x_dt_compat, + .init_late = rk312x_init_late, + .reserve = rk312x_reserve, + .restart = rk312x_restart, +MACHINE_END + diff --git a/include/linux/rockchip/cpu.h b/include/linux/rockchip/cpu.h index b8039ed0f416..069dacb1c5f2 100644 --- a/include/linux/rockchip/cpu.h +++ b/include/linux/rockchip/cpu.h @@ -8,6 +8,7 @@ static inline bool cpu_is_rockchip(void) { return rockchip_soc_id; } #define ROCKCHIP_CPU_MASK 0xffff0000 #define ROCKCHIP_CPU_RK2928 0x29280000 #define ROCKCHIP_CPU_RK3026 0x30260000 +#define ROCKCHIP_CPU_RK3126 0x31260000 #define ROCKCHIP_CPU_RK3036 0x30360000 #define ROCKCHIP_CPU_RK30XX 0x30660000 #define ROCKCHIP_CPU_RK3066B 0x31680000 @@ -17,6 +18,7 @@ static inline bool cpu_is_rockchip(void) { return rockchip_soc_id; } static inline bool cpu_is_rk2928(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK2928; } static inline bool cpu_is_rk3026(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3026; } +static inline bool cpu_is_rk3126(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3126; } static inline bool cpu_is_rk3036(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3036; } static inline bool cpu_is_rk30xx(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK30XX; } static inline bool cpu_is_rk3066b(void) { return (rockchip_soc_id & ROCKCHIP_CPU_MASK) == ROCKCHIP_CPU_RK3066B; } @@ -29,6 +31,8 @@ static inline bool cpu_is_rk3288(void) { return (rockchip_soc_id & ROCKCHIP_CPU #define ROCKCHIP_SOC_RK2928L (ROCKCHIP_CPU_RK2928 | 0x02) #define ROCKCHIP_SOC_RK3028A (ROCKCHIP_CPU_RK3026 | 0x03) #define ROCKCHIP_SOC_RK3026 (ROCKCHIP_CPU_RK3026 | 0x04) +#define ROCKCHIP_SOC_RK3126 (ROCKCHIP_CPU_RK3126 | 0x00) +#define ROCKCHIP_SOC_RK3128 (ROCKCHIP_CPU_RK3126 | 0x01) #define ROCKCHIP_SOC_RK3036 (ROCKCHIP_CPU_RK3036 | 0x00) #define ROCKCHIP_SOC_RK3000 (ROCKCHIP_CPU_RK30XX | 0x00) #define ROCKCHIP_SOC_RK3066 (ROCKCHIP_CPU_RK30XX | 0x01) @@ -46,6 +50,8 @@ static inline bool soc_is_rk2928g(void) { return rockchip_soc_id == ROCKCHIP_SOC static inline bool soc_is_rk2928l(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK2928L; } static inline bool soc_is_rk3028a(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3028A; } static inline bool soc_is_rk3026(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3026; } +static inline bool soc_is_rk3126(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3126; } +static inline bool soc_is_rk3128(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3128; } static inline bool soc_is_rk3036(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3036; } static inline bool soc_is_rk3000(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3000; } static inline bool soc_is_rk3066(void) { return rockchip_soc_id == ROCKCHIP_SOC_RK3066; } diff --git a/include/linux/rockchip/iomap.h b/include/linux/rockchip/iomap.h index 364e2e0914cc..98c552fe856c 100755 --- a/include/linux/rockchip/iomap.h +++ b/include/linux/rockchip/iomap.h @@ -144,4 +144,35 @@ #define RK3036_EFUSE_PHYS 0x20090000 #define RK3036_EFUSE_SIZE SZ_4K +#define RK312X_IMEM_PHYS RK3036_IMEM_PHYS +#define RK312X_IMEM_SIZE RK3036_IMEM_SIZE +#define RK312X_ROM_PHYS RK3036_ROM_PHYS +#define RK312X_ROM_SIZE RK3036_ROM_SIZE +#define RK312X_CPU_AXI_BUS_PHYS RK3036_CPU_AXI_BUS_PHYS +#define RK312X_CPU_AXI_BUS_SIZE RK3036_CPU_AXI_BUS_SIZE +#define RK312X_GIC_DIST_PHYS RK3036_GIC_DIST_PHYS +#define RK312X_GIC_DIST_SIZE RK3036_GIC_DIST_SIZE +#define RK312X_GIC_CPU_PHYS RK3036_GIC_CPU_PHYS +#define RK312X_GIC_CPU_SIZE RK3036_GIC_CPU_SIZE +#define RK312X_CRU_PHYS RK3036_CRU_PHYS +#define RK312X_CRU_SIZE RK3036_CRU_SIZE +#define RK312X_DDR_PCTL_PHYS RK3036_DDR_PCTL_PHYS +#define RK312X_DDR_PCTL_SIZE RK3036_DDR_PCTL_SIZE +#define RK312X_GRF_PHYS RK3036_GRF_PHYS +#define RK312X_GRF_SIZE RK3036_GRF_SIZE +#define RK312X_DDR_PHY_PHYS RK3036_DDR_PHY_PHYS +#define RK312X_DDR_PHY_SIZE RK3036_DDR_PHY_SIZE +#define RK312X_TIMER_PHYS RK3036_TIMER_PHYS +#define RK312X_TIMER_SIZE RK3036_TIMER_SIZE +#define RK312X_UART0_PHYS RK3036_UART0_PHYS +#define RK312X_UART1_PHYS RK3036_UART1_PHYS +#define RK312X_UART2_PHYS RK3036_UART2_PHYS +#define RK312X_UART_SIZE RK3036_UART_SIZE +#define RK312X_GPIO0_PHYS RK3036_GPIO0_PHYS +#define RK312X_GPIO1_PHYS RK3036_GPIO1_PHYS +#define RK312X_GPIO2_PHYS RK3036_GPIO2_PHYS +#define RK312X_GPIO_SIZE RK3036_GPIO_SIZE +#define RK312X_EFUSE_PHYS RK3036_EFUSE_PHYS +#define RK312X_EFUSE_SIZE RK3036_EFUSE_SIZE + #endif