From: Jakob Stoklund Olesen <stoklund@2pi.dk>
Date: Wed, 20 Jun 2012 18:00:57 +0000 (+0000)
Subject: Only update regunit live ranges that have been precomputed.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7824152557cfe3a366963f504b2b956f853ebc3a;p=oota-llvm.git

Only update regunit live ranges that have been precomputed.

Regunit live ranges are computed on demand, so when mi-sched calls
handleMove, some regunits may not have live ranges yet.

That makes updating them easier: Just skip the non-existing ranges. They
will be computed correctly from the rescheduled machine code when they
are needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158831 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index bd3604c4292..bb547c3519a 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -347,6 +347,12 @@ namespace llvm {
       return *LI;
     }
 
+    /// getCachedRegUnit - Return the live range for Unit if it has already
+    /// been computed, or NULL if it hasn't been computed yet.
+    LiveInterval *getCachedRegUnit(unsigned Unit) {
+      return RegUnitIntervals[Unit];
+    }
+
     /// trackingRegUnits - Does LiveIntervals curently track register units?
     /// This function will be removed when regunit tracking is permanently
     /// enabled.
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 6b8cc887043..153d1c37dfd 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -1196,11 +1196,15 @@ private:
       if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
         continue;
 
+      // Collect ranges for register units. These live ranges are computed on
+      // demand, so just skip any that haven't been computed yet.
       if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.trackingRegUnits())
-          for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
-            collectRanges(MO, &LIS.getRegUnit(*Units),
-                          Entering, Internal, Exiting, OldIdx);
-      else if (LIS.hasInterval(Reg))
+        for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
+          if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
+            collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
+
+      // Collect ranges for individual registers.
+      if (LIS.hasInterval(Reg))
         collectRanges(MO, &LIS.getInterval(Reg),
                       Entering, Internal, Exiting, OldIdx);
     }
diff --git a/test/CodeGen/X86/misched-new.ll b/test/CodeGen/X86/misched-new.ll
index 8f2f6f7697d..f7b1467300e 100644
--- a/test/CodeGen/X86/misched-new.ll
+++ b/test/CodeGen/X86/misched-new.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s
+; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup -live-regunits < %s
 ; REQUIRES: asserts
 ;
 ; Interesting MachineScheduler cases.