From: Huang, Tao <huangtao@rock-chips.com>
Date: Fri, 19 Dec 2014 12:02:18 +0000 (+0800)
Subject: Merge tag 'lsk-v3.10-android-14.12'
X-Git-Tag: firefly_0821_release~4158^2~502
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=79437e337230dd5c00df8f88e7c883e39aff5dd0;p=firefly-linux-kernel-4.4.55.git

Merge tag 'lsk-v3.10-android-14.12'

LSK Android 14.12 v3.10

Conflicts:
	include/linux/clk-provider.h
---

79437e337230dd5c00df8f88e7c883e39aff5dd0
diff --cc include/linux/clk-provider.h
index 6ee9fbf109ef,89b7ceed70db..90ad8c2f8e06
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@@ -273,10 -257,8 +273,12 @@@ struct clk_div_table 
   *	Some hardware implementations gracefully handle this case and allow a
   *	zero divisor by not modifying their input clock
   *	(divide by one / bypass).
 + * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
 + *   of this register, and mask of divider bits are in higher 16-bit of this
 + *   register.  While setting the divider bits, higher 16-bit should also be
 + *   updated to indicate changing divider bits.
+  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
+  *	to the closest integer instead of the up one.
   */
  struct clk_divider {
  	struct clk_hw	hw;
@@@ -291,7 -273,7 +293,8 @@@
  #define CLK_DIVIDER_ONE_BASED		BIT(0)
  #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
  #define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
 +#define CLK_DIVIDER_HIWORD_MASK		BIT(3)
+ #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
  
  extern const struct clk_ops clk_divider_ops;
  struct clk *clk_register_divider(struct device *dev, const char *name,