From: Vikram S. Adve <vadve@cs.uiuc.edu>
Date: Thu, 8 Nov 2001 05:15:08 +0000 (+0000)
Subject: Add handle to TargetMachine object in all Machine...Info classes.
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7a2f1e7c5d29682a772af75e78621e6c431e3e4c;p=oota-llvm.git

Add handle to TargetMachine object in all Machine...Info classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1197 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp
index d508b32a399..83bd2f3a3d8 100644
--- a/lib/Target/TargetMachine.cpp
+++ b/lib/Target/TargetMachine.cpp
@@ -49,10 +49,12 @@ TargetMachine::findOptimalStorageSize(const Type* ty) const
 
 
 /*ctor*/
-MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
+MachineInstrInfo::MachineInstrInfo(const TargetMachine& tgt,
+                                   const MachineInstrDescriptor* _desc,
 				   unsigned int _descSize,
 				   unsigned int _numRealOpCodes)
-  : desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
+  : target(tgt),
+    desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
 {
   // FIXME: TargetInstrDescriptors should not be global
   assert(TargetInstrDescriptors == NULL && desc != NULL);
diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp
index 14ac057654d..f9dca290b06 100644
--- a/lib/Target/TargetSchedInfo.cpp
+++ b/lib/Target/TargetSchedInfo.cpp
@@ -78,14 +78,15 @@ ComputeMinGap(const InstrRUsage &fromRU,
 //	Interface to machine description for instruction scheduling
 //---------------------------------------------------------------------------
 
-MachineSchedInfo::MachineSchedInfo(int                     NumSchedClasses,
-                                   const MachineInstrInfo* Mii,
+MachineSchedInfo::MachineSchedInfo(const TargetMachine&    tgt,
+                                   int                     NumSchedClasses,
                                    const InstrClassRUsage* ClassRUsages,
                                    const InstrRUsageDelta* UsageDeltas,
                                    const InstrIssueDelta*  IssueDeltas,
                                    unsigned int		   NumUsageDeltas,
                                    unsigned int		   NumIssueDeltas)
-  : numSchedClasses(NumSchedClasses), mii(Mii),
+  : target(tgt),
+    numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
     classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
     issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
     numIssueDeltas(NumIssueDeltas)