From: Rafael Espindola Date: Wed, 9 Aug 2006 16:41:12 +0000 (+0000) Subject: fix the spill code X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7a53bd0890b0529c6dd95e97611dca7a8c4d6077;p=oota-llvm.git fix the spill code git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29583 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 1ef5bf48ca6..8d2cbfd5bb5 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -148,6 +148,12 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) { Ops.push_back(Chain); Ops.push_back(Callee); + // Add argument registers to the end of the list so that they are known live + // into the call. + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) + Ops.push_back(DAG.getRegister(RegsToPass[i].first, + RegsToPass[i].second.getValueType())); + unsigned CallOpc = ARMISD::CALL; if (InFlag.Val) Ops.push_back(InFlag); diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 9c607691eaa..ba0cd916e85 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -31,9 +31,8 @@ void ARMRegisterInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int FI, const TargetRegisterClass *RC) const { - // On the order of operands here: think "[FI + 0] = SrcReg". assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg); + BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI); } void ARMRegisterInfo:: @@ -41,7 +40,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC) const { assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0); + BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI); } void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, @@ -81,7 +80,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - assert (MI.getOpcode() == ARM::ldr); + assert (MI.getOpcode() == ARM::ldr || + MI.getOpcode() == ARM::str); unsigned FrameIdx = 2; unsigned OffIdx = 1; @@ -93,6 +93,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { unsigned StackSize = MF.getFrameInfo()->getStackSize(); + // + if (Offset < 0) + Offset -= 4; + // + Offset += StackSize; assert (Offset >= 0); @@ -121,9 +126,6 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); int NumBytes = (int) MFI->getStackSize(); - //hack - assert(NumBytes == 0); - if (MFI->hasCalls()) { // We reserve argument space for call sites in the function immediately on // entry to the current function. This eliminates the need for add/sub diff --git a/test/CodeGen/ARM/vargs.ll b/test/CodeGen/ARM/vargs.ll index 858c463c58d..f60c51a3c96 100644 --- a/test/CodeGen/ARM/vargs.ll +++ b/test/CodeGen/ARM/vargs.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -march=arm +; RUN: llvm-as < %s | llc -march=arm %str = internal constant [43 x sbyte] c"Hello World %d %d %d %d %d %d %d %d %d %d\0A\00" ; <[43 x sbyte]*> [#uses=1] implementation ; Functions: @@ -6,7 +6,8 @@ implementation ; Functions: int %main() { entry: %tmp = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([43 x sbyte]* %str, int 0, uint 0), int 1, int 2, int 3, int 4, int 5, int 6, int 7, int 8, int 9, int 10 ) ; [#uses=0] - ret int 0 + %tmp2 = call int (sbyte*, ...)* %printf( sbyte* getelementptr ([43 x sbyte]* %str, int 0, uint 0), int 10, int 9, int 8, int 7, int 6, int 5, int 4, int 3, int 2, int 1 ) ; [#uses=0] + ret int 11 } declare int %printf(sbyte*, ...)