From: Ingo Molnar Date: Tue, 28 Oct 2008 15:26:12 +0000 (+0100) Subject: Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks X-Git-Tag: firefly_0821_release~16487^2~4^21 X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7a9787e1eba95a166265e6a260cf30af04ef0a99;p=firefly-linux-kernel-4.4.55.git Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks --- 7a9787e1eba95a166265e6a260cf30af04ef0a99 diff --cc arch/x86/include/asm/io_apic.h index 000000000000,6afd9933a7dd..e475e009ae5d mode 000000,100644..100644 --- a/arch/x86/include/asm/io_apic.h +++ b/arch/x86/include/asm/io_apic.h @@@ -1,0 -1,204 +1,214 @@@ + #ifndef _ASM_X86_IO_APIC_H + #define _ASM_X86_IO_APIC_H + + #include + #include + #include + #include + + /* + * Intel IO-APIC support for SMP and UP systems. + * + * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar + */ + + /* I/O Unit Redirection Table */ + #define IO_APIC_REDIR_VECTOR_MASK 0x000FF + #define IO_APIC_REDIR_DEST_LOGICAL 0x00800 + #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000 + #define IO_APIC_REDIR_SEND_PENDING (1 << 12) + #define IO_APIC_REDIR_REMOTE_IRR (1 << 14) + #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15) + #define IO_APIC_REDIR_MASKED (1 << 16) + + /* + * The structure of the IO-APIC: + */ + union IO_APIC_reg_00 { + u32 raw; + struct { + u32 __reserved_2 : 14, + LTS : 1, + delivery_type : 1, + __reserved_1 : 8, + ID : 8; + } __attribute__ ((packed)) bits; + }; + + union IO_APIC_reg_01 { + u32 raw; + struct { + u32 version : 8, + __reserved_2 : 7, + PRQ : 1, + entries : 8, + __reserved_1 : 8; + } __attribute__ ((packed)) bits; + }; + + union IO_APIC_reg_02 { + u32 raw; + struct { + u32 __reserved_2 : 24, + arbitration : 4, + __reserved_1 : 4; + } __attribute__ ((packed)) bits; + }; + + union IO_APIC_reg_03 { + u32 raw; + struct { + u32 boot_DT : 1, + __reserved_1 : 31; + } __attribute__ ((packed)) bits; + }; + + enum ioapic_irq_destination_types { + dest_Fixed = 0, + dest_LowestPrio = 1, + dest_SMI = 2, + dest__reserved_1 = 3, + dest_NMI = 4, + dest_INIT = 5, + dest__reserved_2 = 6, + dest_ExtINT = 7 + }; + + struct IO_APIC_route_entry { + __u32 vector : 8, + delivery_mode : 3, /* 000: FIXED + * 001: lowest prio + * 111: ExtINT + */ + dest_mode : 1, /* 0: physical, 1: logical */ + delivery_status : 1, + polarity : 1, + irr : 1, + trigger : 1, /* 0: edge, 1: level */ + mask : 1, /* 0: enabled, 1: disabled */ + __reserved_2 : 15; + + __u32 __reserved_3 : 24, + dest : 8; + } __attribute__ ((packed)); + + struct IR_IO_APIC_route_entry { + __u64 vector : 8, + zero : 3, + index2 : 1, + delivery_status : 1, + polarity : 1, + irr : 1, + trigger : 1, + mask : 1, + reserved : 31, + format : 1, + index : 15; + } __attribute__ ((packed)); + + #ifdef CONFIG_X86_IO_APIC + + /* + * # of IO-APICs and # of IRQ routing registers + */ + extern int nr_ioapics; + extern int nr_ioapic_registers[MAX_IO_APICS]; + + /* + * MP-BIOS irq configuration table structures: + */ + + #define MP_MAX_IOAPIC_PIN 127 + + struct mp_config_ioapic { + unsigned long mp_apicaddr; + unsigned int mp_apicid; + unsigned char mp_type; + unsigned char mp_apicver; + unsigned char mp_flags; + }; + + struct mp_config_intsrc { + unsigned int mp_dstapic; + unsigned char mp_type; + unsigned char mp_irqtype; + unsigned short mp_irqflag; + unsigned char mp_srcbus; + unsigned char mp_srcbusirq; + unsigned char mp_dstirq; + }; + + /* I/O APIC entries */ + extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; + + /* # of MP IRQ source entries */ + extern int mp_irq_entries; + + /* MP IRQ source entries */ + extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; + + /* non-0 if default (table-less) MP configuration */ + extern int mpc_default_type; + + /* Older SiS APIC requires we rewrite the index register */ + extern int sis_apic_bug; + + /* 1 if "noapic" boot option passed */ + extern int skip_ioapic_setup; + ++/* 1 if "noapic" boot option passed */ ++extern int noioapicquirk; ++ ++/* -1 if "noapic" boot option passed */ ++extern int noioapicreroute; ++ + /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ + extern int timer_through_8259; + + static inline void disable_ioapic_setup(void) + { ++#ifdef CONFIG_PCI ++ noioapicquirk = 1; ++ noioapicreroute = -1; ++#endif + skip_ioapic_setup = 1; + } + + /* + * If we use the IO-APIC for IRQ routing, disable automatic + * assignment of PCI IRQ's. + */ + #define io_apic_assign_pci_irqs \ + (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs) + + #ifdef CONFIG_ACPI + extern int io_apic_get_unique_id(int ioapic, int apic_id); + extern int io_apic_get_version(int ioapic); + extern int io_apic_get_redir_entries(int ioapic); + extern int io_apic_set_pci_routing(int ioapic, int pin, int irq, + int edge_level, int active_high_low); + #endif /* CONFIG_ACPI */ + + extern int (*ioapic_renumber_irq)(int ioapic, int irq); + extern void ioapic_init_mappings(void); + + #ifdef CONFIG_X86_64 + extern int save_mask_IO_APIC_setup(void); + extern void restore_IO_APIC_setup(void); + extern void reinit_intr_remapped_IO_APIC(int); + #endif + + extern int probe_nr_irqs(void); + + #else /* !CONFIG_X86_IO_APIC */ + #define io_apic_assign_pci_irqs 0 + static const int timer_through_8259 = 0; + static inline void ioapic_init_mappings(void) { } + + static inline int probe_nr_irqs(void) + { + return NR_IRQS; + } + #endif + + #endif /* _ASM_X86_IO_APIC_H */ diff --cc arch/x86/include/asm/pci.h index 000000000000,875b38edf193..647781298e7e mode 000000,100644..100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@@ -1,0 -1,114 +1,116 @@@ + #ifndef _ASM_X86_PCI_H + #define _ASM_X86_PCI_H + + #include /* for struct page */ + #include + #include + #include + #include + #include + + #ifdef __KERNEL__ + + struct pci_sysdata { + int domain; /* PCI domain */ + int node; /* NUMA node */ + #ifdef CONFIG_X86_64 + void *iommu; /* IOMMU private data */ + #endif + }; + + extern int pci_routeirq; ++extern int noioapicquirk; ++extern int noioapicreroute; + + /* scan a bus after allocating a pci_sysdata for it */ + extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, + int node); + extern struct pci_bus *pci_scan_bus_with_sysdata(int busno); + + static inline int pci_domain_nr(struct pci_bus *bus) + { + struct pci_sysdata *sd = bus->sysdata; + return sd->domain; + } + + static inline int pci_proc_domain(struct pci_bus *bus) + { + return pci_domain_nr(bus); + } + + + /* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + + #ifdef CONFIG_PCI + extern unsigned int pcibios_assign_all_busses(void); + #else + #define pcibios_assign_all_busses() 0 + #endif + #define pcibios_scan_all_fns(a, b) 0 + + extern unsigned long pci_mem_start; + #define PCIBIOS_MIN_IO 0x1000 + #define PCIBIOS_MIN_MEM (pci_mem_start) + + #define PCIBIOS_MIN_CARDBUS_IO 0x4000 + + void pcibios_config_init(void); + struct pci_bus *pcibios_scan_root(int bus); + + void pcibios_set_master(struct pci_dev *dev); + void pcibios_penalize_isa_irq(int irq, int active); + struct irq_routing_table *pcibios_get_irq_routing_table(void); + int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq); + + + #define HAVE_PCI_MMAP + extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, + enum pci_mmap_state mmap_state, + int write_combine); + + + #ifdef CONFIG_PCI + extern void early_quirks(void); + static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) + { + *strat = PCI_DMA_BURST_INFINITY; + *strategy_parameter = ~0UL; + } + #else + static inline void early_quirks(void) { } + #endif + + #endif /* __KERNEL__ */ + + #ifdef CONFIG_X86_32 + # include "pci_32.h" + #else + # include "pci_64.h" + #endif + + /* implement the pci_ DMA API in terms of the generic device dma_ one */ + #include + + /* generic pci stuff */ + #include + + #ifdef CONFIG_NUMA + /* Returns the node based on pci bus */ + static inline int __pcibus_to_node(struct pci_bus *bus) + { + struct pci_sysdata *sd = bus->sysdata; + + return sd->node; + } + + static inline cpumask_t __pcibus_to_cpumask(struct pci_bus *bus) + { + return node_to_cpumask(__pcibus_to_node(bus)); + } + #endif + + #endif /* _ASM_X86_PCI_H */ diff --cc include/linux/pci.h index cfc2297c3e28,c75b82bda327..9194adf82e20 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@@ -124,13 -130,10 +130,15 @@@ enum pci_dev_flags * generation too. */ PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1, + /* Device configuration is irrevocably lost if disabled into D3 */ + PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2, }; +enum pci_irq_reroute_variant { + INTEL_IRQ_REROUTE_VARIANT = 1, + MAX_IRQ_REROUTE_VARIANTS = 3 +}; + typedef unsigned short __bitwise pci_bus_flags_t; enum pci_bus_flags { PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, @@@ -215,9 -218,9 +223,10 @@@ struct pci_dev unsigned int no_msi:1; /* device may not use msi */ unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ unsigned int broken_parity_status:1; /* Device generates false positive parity */ + unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ unsigned int msi_enabled:1; unsigned int msix_enabled:1; + unsigned int ari_enabled:1; /* ARI forwarding */ unsigned int is_managed:1; unsigned int is_pcie:1; pci_dev_flags_t dev_flags;