From: Matthias Braun Date: Thu, 29 Oct 2015 05:06:41 +0000 (+0000) Subject: Revert "ScheduleDAGInstrs: Remove IsPostRA flag" X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7b38ebfa478a5931fe4b27ea40c3eabbd2bf53e7;p=oota-llvm.git Revert "ScheduleDAGInstrs: Remove IsPostRA flag" It broke 3 arm testcases. This reverts commit r251608. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251615 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index c5c905571ee..9d3212e3e9d 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -254,8 +254,9 @@ protected: #endif public: ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr S, - bool RemoveKillFlags) - : ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags, C->LIS), + bool IsPostRA) + : ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA, + /*RemoveKillFlags=*/IsPostRA, C->LIS), AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(), CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) { #ifndef NDEBUG @@ -385,7 +386,7 @@ protected: public: ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr S) - : ScheduleDAGMI(C, std::move(S), /*RemoveKillFlags=*/false), + : ScheduleDAGMI(C, std::move(S), /*IsPostRA=*/false), RegClassInfo(C->RegClassInfo), DFSResult(nullptr), ShouldTrackPressure(false), RPTracker(RegPressure), TopRPTracker(TopPressure), BotRPTracker(BotPressure) {} diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index f8c225a1255..b56d5ec8ce6 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -84,6 +84,9 @@ namespace llvm { /// TargetSchedModel provides an interface to the machine model. TargetSchedModel SchedModel; + /// isPostRA flag indicates vregs cannot be present. + bool IsPostRA; + /// True if the DAG builder should remove kill flags (in preparation for /// rescheduling). bool RemoveKillFlags; @@ -151,11 +154,14 @@ namespace llvm { public: explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, + bool IsPostRAFlag, bool RemoveKillFlags = false, LiveIntervals *LIS = nullptr); ~ScheduleDAGInstrs() override {} + bool isPostRA() const { return IsPostRA; } + /// \brief Expose LiveIntervals for use in DAG mutators and such. LiveIntervals *getLIS() const { return LIS; } diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index d65e0f457dc..2b36b2b1c0a 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -111,7 +111,7 @@ public: void print(raw_ostream &O, const Module* = nullptr) const override; protected: - void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags); + void scheduleRegions(ScheduleDAGInstrs &Scheduler); }; /// MachineScheduler runs after coalescing and before register allocation. @@ -340,7 +340,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { // Instantiate the selected scheduler for this target, function, and // optimization level. std::unique_ptr Scheduler(createMachineScheduler()); - scheduleRegions(*Scheduler, false); + scheduleRegions(*Scheduler); DEBUG(LIS->dump()); if (VerifyScheduling) @@ -368,7 +368,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { // Instantiate the selected scheduler for this target, function, and // optimization level. std::unique_ptr Scheduler(createPostMachineScheduler()); - scheduleRegions(*Scheduler, true); + scheduleRegions(*Scheduler); if (VerifyScheduling) MF->verify(this, "After post machine scheduling."); @@ -388,14 +388,15 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { static bool isSchedBoundary(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, - const TargetInstrInfo *TII) { + const TargetInstrInfo *TII, + bool IsPostRA) { return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF); } /// Main driver for both MachineScheduler and PostMachineScheduler. -void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, - bool FixKillFlags) { +void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler) { const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); + bool IsPostRA = Scheduler.isPostRA(); // Visit all machine basic blocks. // @@ -433,7 +434,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, // Avoid decrementing RegionEnd for blocks with no terminator. if (RegionEnd != MBB->end() || - isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII)) { + isSchedBoundary(&*std::prev(RegionEnd), &*MBB, MF, TII, IsPostRA)) { --RegionEnd; // Count the boundary instruction. --RemainingInstrs; @@ -444,7 +445,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, unsigned NumRegionInstrs = 0; MachineBasicBlock::iterator I = RegionEnd; for(;I != MBB->begin(); --I, --RemainingInstrs) { - if (isSchedBoundary(&*std::prev(I), &*MBB, MF, TII)) + if (isSchedBoundary(&*std::prev(I), &*MBB, MF, TII, IsPostRA)) break; if (!I->isDebugValue()) ++NumRegionInstrs; @@ -460,7 +461,8 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, Scheduler.exitRegion(); continue; } - DEBUG(dbgs() << "********** MI Scheduling **********\n"); + DEBUG(dbgs() << "********** " << ((Scheduler.isPostRA()) ? "PostRA " : "") + << "MI Scheduling **********\n"); DEBUG(dbgs() << MF->getName() << ":BB#" << MBB->getNumber() << " " << MBB->getName() << "\n From: " << *I << " To: "; @@ -487,11 +489,11 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler, } assert(RemainingInstrs == 0 && "Instruction count mismatch!"); Scheduler.finishBlock(); - // FIXME: Ideally, no further passes should rely on kill flags. However, - // thumb2 size reduction is currently an exception, so the PostMIScheduler - // needs to do this. - if (FixKillFlags) - Scheduler.fixupKills(&*MBB); + if (Scheduler.isPostRA()) { + // FIXME: Ideally, no further passes should rely on kill flags. However, + // thumb2 size reduction is currently an exception. + Scheduler.fixupKills(&*MBB); + } } Scheduler.finalizeSchedule(); } diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 9fb4edfa587..c56b0ec143a 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -51,12 +51,15 @@ static cl::opt UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, - bool RemoveKillFlags, + bool IsPostRAFlag, bool RemoveKillFlags, LiveIntervals *lis) : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis), - RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false), - FirstDbgValue(nullptr) { + IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags), + CanHandleTerminators(false), FirstDbgValue(nullptr) { + assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); DbgValues.clear(); + assert(!(IsPostRA && MRI.getNumVirtRegs()) && + "Virtual registers must be removed prior to PostRA scheduling"); const TargetSubtargetInfo &ST = mf.getSubtarget(); SchedModel.init(ST.getSchedModel(), &ST, TII); @@ -227,8 +230,11 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() { if (TRI->isPhysicalRegister(Reg)) Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); - else if (MO.readsReg()) // ignore undef operands - addVRegUseDeps(&ExitSU, i); + else { + assert(!IsPostRA && "Virtual register encountered after regalloc."); + if (MO.readsReg()) // ignore undef operands + addVRegUseDeps(&ExitSU, i); + } } } else { // For others, e.g. fallthrough, conditional branch, assume the exit @@ -825,6 +831,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, if (TRI->isPhysicalRegister(Reg)) addPhysRegDeps(SU, j); else { + assert(!IsPostRA && "Virtual register encountered!"); if (MO.isDef()) { HasVRegDef = true; addVRegDefDeps(SU, j);