From: Chris Lattner <sabre@nondot.org>
Date: Wed, 2 Nov 2005 01:47:04 +0000 (+0000)
Subject: Fix a source of undefined behavior when dealing with 64-bit types. This
X-Git-Url: http://demsky.eecs.uci.edu/git/?a=commitdiff_plain;h=7c22575e3292a80b42ec6189d618976a464f7406;p=oota-llvm.git

Fix a source of undefined behavior when dealing with 64-bit types. This
may fix PR652.  Thanks to Andrew for tracking down the problem.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24145 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 048737f13e2..b4bd5aa0b42 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -384,7 +384,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
     return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
   case ISD::ZERO_EXTEND:
     SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
-    return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
+    return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits)),TLI);
   case ISD::AssertZext:
     SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
     return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.